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VLSI
Solution
y
VS1103b
VS1103B
5. SPI BUSES
5.6 SPI Timing Diagram
XCS
SCK
SI
SO
0
1
15
14
16
tXCSS
tXCSH
tWL
tWH
tH
tSU
tV
tZ
tDIS
tXCS
30
31
Figure 8: SPI Timing Diagram.
Symbol
Min
Max
Unit
tXCSS
5
ns
tSU
-26
ns
tH
2
CLKI cycles
tZ
0
ns
tWL
2
CLKI cycles
tWH
2
CLKI cycles
tV
2 (+ 25ns1)
CLKI cycles
tXCSH
-26
ns
tXCS
2
CLKI cycles
tDIS
10
ns
1 25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance.
Note: As tWL and tWH, as well as tH require at least 2 clock cycles, the maximum speed for the SPI
bus that can easily be used is 1/6 of VS1103b’s internal clock speed CLKI. Slightly higher speed can be
achieved with very careful timing tuning. For details, see Application Notes for VS10XX.
Note: Although the timing is derived from the internal clock CLKI, the system always starts up in 1.0×
mode, thus CLKI=XTALI.
Note: Negative numbers mean that the signal can change in different order from what is shown in the
diagram.
Version 1.01, 2007-09-03
20
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