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VLSI
Solution
y
VS1103b
VS1103B
5. SPI BUSES
5.5.2 SCI Read
0
1
2
3
4
5
6
7
8
9
10 11 12 13
30 31
14 15 16 17
0
0
0
0
0
0
1
1
0
0
0
0
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15 14
1
0
X
instruction (read)
address
data out
XCS
SCK
SI
SO
don’t care
don’t care
DREQ
execution
Figure 5: SCI Word Read
VS1103b registers are read from using the following sequence, as shown in Figure 5. First, XCS line is
pulled low to select the device. Then the READ opcode (0x3) is transmitted via the SI line followed by
an 8-bit word address. After the address has been read in, any further data on SI is ignored by the chip.
The 16-bit data corresponding to the received address will be shifted out onto the SO line.
XCS should be driven high after data has been shifted out.
DREQ is driven low for a short while when in a read operation by the chip. This is a very short time and
doesn’t require special user attention.
5.5.3 SCI Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13
30 31
14 15 16 17
0
0
0
0
0
0
1
0
0
0
0
3
2
1
0
1
0
X
address
XCS
SCK
SI
15 14
data out
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SO
0
0
0
0 X
0
instruction (write)
DREQ
execution
Figure 6: SCI Word Write
VS1103b registers are written from using the following sequence, as shown in Figure 6. First, XCS line
is pulled low to select the device. Then the WRITE opcode (0x2) is transmitted via the SI line followed
by an 8-bit word address.
Version 1.01, 2007-09-03
18
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