CC2550-RTY1 datasheet(15/62 Pages) TI2

15 / 62 page

CC2550

SWRS039B

Page 15 of 58

DW 7

Read from register:

Write to register:

Hi-Z

SCLK:

CSn:

SO Hi-Z

Hi-Z

DW6DW5DW4DW3DW2DW 1DW 0

BS5

A5A4

A3A2A1A0

S4S3S2S1S0

DR7DR 6DR 5DR 4DR 3DR 2DR 1DR0

Figure 6: Configuration Registers Write and Read Operations

Parameter

Description

Min

Max

Units

SCLK

frequency

100 ns delay inserted between address byte and data byte (single access), or between

address and data, and between each data byte (burst access).

MHz

SCLK

frequency, single access

No delay between address and data byte

MHz

fSCLK

SCLK

frequency, burst access

No delay between address and data byte, or between data bytes

6.5

MHz

tsp,pd

CSn

low to positive edge on SCLK, in power-down mode

150

µs

tsp

CSn

low to positive edge on SCLK, in active mode

tch

Clock high

tcl

Clock low

trise

Clock rise time

tfall

Clock fall time

Single access

tsd

Setup data (negative SCLK edge) to

positive edge on SCLK

(tsd applies between address and data bytes, and

between data bytes)

Burst access

thd

Hold data after positive edge on SCLK

tns

Negative edge on SCLK to CSn high

Table 14: SPI Interface Timing Requirements

Note:

The minimum tsp,pd figure in Table 14 can be used in cases where the user does not read the

CHIP_RDYn

signal. CSn low to positive edge on SCLK when the chip is woken from power-down

depends on the start-up time of the crystal being used. The 150 us in Table 14 is the crystal oscillator

start-up time measured on CC2550EM reference design ([3]) using crystal AT-41CD2 from NDK.

10.1

Chip Status Byte

When the header byte, data byte, or command

strobe is sent on the SPI interface, the chip

status byte is sent by the

CC2550 on the SO

pin. The status byte contains key status

signals, useful for the MCU. The first bit, s7, is

the CHIP_RDYn signal; this signal must go low

before the first positive edge of SCLK. The

CHIP_RDYn

signal indicates that the crystal is

running.

Bits 6, 5, and 4 comprise the STATE value.

This value reflects the state of the chip. The

XOSC and power to the digital core is on in the

IDLE state, but all other modules are in power

CC2550-RTY1 数据表(PDF) 15 Page - Texas Instruments

CC2550-RTY1 数据表(HTML) 15 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表下载

链接网址

CC2550-RTY1 数据表(PDF) 15 Page - Texas Instruments

CC2550-RTY1 数据表(HTML) 15 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表 下载

链接网址

数据表下载