CC2550-RTY1 datasheet(55/62 Pages) TI2

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CC2550

SWRS039B

Page 55 of 58

General Information

32.1

Document History

Revision

Date

Description/Changes

SWRS039B

2007-09-30 kbps replaced by kBaud throughout the document.

Some of the sections hav been re-written to be easier to read without having any new

info added.

Absolute maximum supply voltage rating increased from 3.6 V to 3.9 V.

FSK changed to 2-FSK throughout the document.

Updates to the Abbreviation table.

Updates to the Electrical Specifications section. Added ACP and OBW performance.

Added info about TX latency in serial mode.

Added info about default values after reset versus optimum register settings in the

Configuration Software section.

Changes to the SPI Interface Timing Requirements. Info added about tsp,pd

The following figures have been changed: Configuration Registers Write and Read

Operations, SRES Command Strobe, and Register Access Types.

In the Register Access section, the address range is changed.

Changes to PATABLE Access section.

In the Packet Format section, preamble pattern is changed to 10101010 and info

about bug related to turning off the transmitter in infinite packet length mode is added.

Added info about the initial value of the PN9 sequence in the Data Whitening section.

Added info about TX FIFO underflow state in the Packet Handling in Transmit Mode

section.

Added section Packet Handling in Firmware.

Removed all references to the voltage regulator in relation with the CHP_RDYn

signal, as this signal is only related to the crystal.

Removed references to the voltage regulator in the figures: Power-On Reset and

Power-On Reset with SRES. Changes to the SI line in the Power-On Reset with

SRES figure.

Added info on the three automatic calibration options.

The Output Power Programming section has been changed. Only 1 PATABLE entry

used for 2-FSK/GFSK/MSK and 2 PATABLE entries used for OOK. Added info about

PATABLE when entering SLEEP mode. New PA_POWER and PATABLE figure.

Added section on PCB Layout Recommendations.

In section General Purpose / Test Output Control Pins: Added info on GDO pins in

SLEEP state.

Asynchronous transparent mode is called asynchronous serial mode throughout the

document.

Removed comments about having to use NRZ coding in synchronous serial mode.

Added info that Manchester encoding cannot be used in asynchronous serial mode.

Changed field name and/or description of the following registers:

MCSM0, FSCAL3, FSCAL2, FSCAL1 and TEST0.

Added references.

1.2

SWRS039A

2006-06-28 Added figures to table on SPI interface timing requirements.

Added information about SPI read.

Updates to text and included new figure in section on arbitrary length configuration.

Added information that RF frequencies at n/2·crystal frequency (n is an integer

number) should not be used due to spurious signals at these frequencies .

Updates to text and included new figures in section on power-on start-up sequence.

Added information about how to check for PLL lock in section on VCO.

Better explanation of some of the signals in table of GDO signal selection.

Added section on wideband modulation not using spread spectrum under section on

system considerations and guidelines.

Added more detailed information on PO_TIMEOUT in register MCSM0.

Changes to ordering information.

1.1

2005-06-27 Updated TEST1 register default value. 26-27 MHz crystal range. Added matching

information. Added information about using a reference signal instead of a crystal.

1.0

2005-01-24 First preliminary data sheet release.

Table 32: Document History

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