CC2550-RTY1 datasheet(28/62 Pages) TI2

28 / 62 page

CC2550

SWRS039B

Page 28 of 58

viewed on the GDO pins (see Section 25 on

page 33).

Figure 17 shows the number of bytes in the TX

FIFO when the threshold flag toggles, in the

case of FIFO_THR=13. Figure 16 shows the

signal as the FIFO is filled above the

threshold, and then drained below.

NUM_TXBYTES

GDO

Figure 16: FIFO_THR=13 vs. Number of

Bytes in FIFO (GDOx_CFG=0x02)

FIFO_THR

Bytes in TX FIFO

0 (0000)

1 (0001)

2 (0010)

3 (0011)

4 (0100)

5 (0101)

6 (0110)

7 (0111)

8 (1000)

9 (1001)

10 (1010)

11 (1011)

12 (1100)

13 (1101)

14 (1110)

15 (1111)

Table 19: FIFO_THR Settings and the

Corresponding FIFO Thresholds

8 bytes

Underflow

margin

FIFO_THR=13

TXFIFO

Figure 17: Example of FIFO at Threshold

Frequency Programming

The frequency programming in

CC2550 is

designed

minimize

the

programming

needed in a channel-oriented system.

To set up a system with channel numbers, the

desired channel spacing is programmed with

the

MDMCFG0.CHANSPC_M

and

MDMCFG1.CHANSPC_E

registers. The channel

spacing registers are mantissa and exponent

respectively.

The base or start frequency is set by the 24 bit

frequency word located in the FREQ2, FREQ1

and FREQ0 registers. This word will typically

be set to the centre of the lowest channel

frequency that is to be used.

The desired channel number is programmed

with the 8-bit channel number register,

CHANNR.CHAN

, which is multiplied by the

channel offset. The resultant carrier frequency

is given by:

()

(

)

()

256

−

⋅

CHANSPC

XOSC

carrier

CHANSPC

CHAN

FREQ

CC2550-RTY1 数据表(PDF) 28 Page - Texas Instruments

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