CC2550-RTY1 datasheet(37/62 Pages) TI2

37 / 62 page

CC2550

SWRS039B

Page 37 of 58

27.9

Increasing Output Power

In some applications it may be necessary to

extend the link range by adding an external

power amplifier.

The power amplifier should be inserted

between the antenna and the balun as shown

in Figure 22.

Figure 22: Block Diagram of

CC2550 Usage with External Power Amplifier

Configuration Registers

The configuration of

CC2550 is done by

programming 8-bit registers. The optimum

configuration data based on selected system

parameters are most easily found by using the

SmartRF® Studio software [4]. Complete

descriptions of the registers are given in the

following tables. After chip reset, all the

registers have default values as shown in the

tables. The optimum register setting might

differ from the default value. After a reset all

registers that shall be different from the default

value therefore needs to be programmed

through the SPI interface.

There are 9 command strobe registers, listed

in Table 23. Accessing these registers will

initiate the change of an internal state or

mode. There are 29 normal 8-bit configuration

registers, listed in Table 24. Some of these

registers are for test purposes only, and need

not be written for normal operation of

CC2550.

There are also 6 status registers, which are

listed in Table 25. These registers, which are

read-only, contain information about the status

CC2550.

The TX FIFO is accessed through one 8-bit

the TX FIFO.

During the header byte transfer and while

writing data to a register or the TX FIFO, a

status byte is returned on the SO line. This

status byte is described in Table 15 on page

16.

Table 26 summarizes the SPI address space.

Registers that are only defined in the

CC2500

transceiver are also listed.

CC2500 and CC2550

are register compatible, but registers and fields

only implemented in the transceiver always

contain 0 in

CC2550. The address to use is

given by adding the base address to the left

and the burst and R/W bits on the top. Note

that the burst bit has different meaning for

base addresses above and below 0x2F.

Note that all registers, (with the exception of

the MSCM0.PO_TIMEOUT field) will lose their

content in SLEEP mode.

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