CC2550-RTY1 datasheet(35/62 Pages) TI2

35 / 62 page

CC2550

SWRS039B

Page 35 of 58

transfer is also included in

CC2550. When

asynchronous transfer is enabled, several of

the support mechanisms for the MCU that are

included in

CC2550 will be disabled, such as

packet handling hardware, buffering in the

FIFO and so on. The asynchronous transfer

mode does not allow the use of the data

whitener, interleaver and FEC, and it is not

possible to use Manchester encoding.

Note

that

MSK

not

supported

for

asynchronous transfer.

Setting

PKTCTRL0.PKT_FORMAT

enables asynchronous serial mode.

The GDO0 pin is used for data input (TX data).

The

CC2550 modulator samples the level of the

asynchronous input 8 times faster than the

programmed data rate. The timing requirement

for the asynchronous stream is that the error in

the bit period must be less than one eighth of

the programmed data rate.

26.2

Synchronous Serial Operation

Setting

PKTCTRL0.PKT_FORMAT

enables synchronous serial operation mode. In

the synchronous mode, data is transferred on

a two wire serial interface. The

CC2550

provides a clock that is used to set up new

data on the data input line. Data input (TX

data) is the GDO0 pin. This pin will

automatically be configured as an input when

TX is active.

Preamble and sync word insertion may or may

not be active, dependent on the sync mode set

by the MDMCFG3.SYNC_MODE. If preamble and

sync word is disabled, all other packet handler

features and FEC should also be disabled.

The MCU must then handle preamble and

sync word insertion in software. If preamble

and sync word insertion is left on, all packet

handling features and FEC can be used.

When using the packet handling features in

synchronous serial mode, the

CC2550 will

insert the preamble and sync word and the

MCU will only provide the data payload. This is

equivalent

the

recommended

FIFO

operation mode.

27 System considerations and Guidelines

27.1

SRD Regulations

International regulations and national laws

regulate the use of radio receivers and

transmitters. The most important regulations

for the 2.4 Ghz band are EN 300 440 and EN

300 328 (Europe), FCC CFR47 part 15.247

and 15.249 (USA), and ARIB STD-T66

(Japan). A summary of the most important

aspects of these regulations can be found in

Application Note AN032 [2].

Please note that compliance with regulations

dependent

complete

system

performance. It is the customer’s responsibility

to ensure that the system complies with

regulations.

27.2

Frequency

Hopping

and

Multi-

Channel Systems

The 2.400 – 2.4835 GHz band is shared by

many systems both in industrial, office and

home

environments.

therefore

recommended to use frequency hopping

spread spectrum (FHSS) or a multi-channel

protocol because the frequency diversity

makes the system more robust with respect to

interference from other systems operating in

the same frequency band. FHSS also combats

multipath fading.

CC2550 is highly suited for FHSS or multi-

channel systems due to its agile frequency

synthesizer

and

effective

communication

interface. Using the packet handling support

and data buffering is also beneficial in such

systems as these features will significantly

offload the host controller.

Charge pump current, VCO current and VCO

capacitance array calibration data is required

for

each

frequency

when

implementing

frequency hopping for

CC2550. There are 3

ways of obtaining the calibration data from the

chip:

1) Frequency hopping with calibration for each

hop. The PLL calibration time is approximately

720 µs. The blanking interval between each

frequency hop is then approximately 810 us.

2) Fast frequency hopping without calibration

for each hop can be done by calibrating each

frequency at startup and saving the resulting

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