CC2550-RTY1 datasheet(16/62 Pages) TI2

16 / 62 page

CC2550

SWRS039B

Page 16 of 58

down.

The

frequency

and

channel

configuration should only be updated when the

chip is in this state. The TX state is active

when the chip is transmitting.

The last four bits (3:0) in the status byte

contains FIFO_BYTES_AVAILABLE. For write

operations (the R/W bit in the header byte is

set to 0), the FIFO_BYTES_AVAILABLE field

contains the number of bytes that can be

written

the

FIFO.

When

FIFO_BYTES_AVAILABLE

=15, 15 or more

bytes are available/free.

Table 15 gives a status byte summary.

Bits

Name

Description

CHIP_RDYn

Stays high until power and crystal have stabilized. Should always be low when using

the SPI interface.

6:4

STATE[2:0]

Indicates the current main state machine mode

Value

State

Description

000

IDLE

Idle state

(Also reported for some transitional states

instead of SETTLING or CALIBRATE)

001

Not used

010

Transmit mode

011

FSTXON

Frequency synthesizer is on, ready to start

transmitting

100

CALIBRATE

Frequency synthesizer calibration is running

101

SETTLING

PLL is settling

110

Not used

111

TXFIFO_UNDERFLOW

TX FIFO has underflowed. Acknowledge with

SFTX

3:0

FIFO_BYTES_AVAILABLE[3:0]

The number of free bytes in the TX FIFO (the R/W bit in the header byte must be set

to 0)

Table 15: Status Byte Summary

10.2

Registers Access

The configuration registers on the

CC2550 are

located on SPI addresses from 0x00 to 0x2E.

Table 24 on page 39 lists all configuration

registers. It is highly recommended to use

SmartRF

Studio [4] to generate optimum

each register is found in Section 28.1, starting

on page 41. All configuration registers can be

both written to and read. The R/W bit controls

if the register should be written to or read.

When writing to registers, the status byte is

sent on the SO pin each time a header byte or

data byte is transmitted on the SI pin. When

reading from registers, the status byte is sent

on the SO pin each time a header byte is

transmitted on the SI pin.

Registers with consecutive addresses can be

accessed in an efficient way by setting the

burst bit (B) in the header byte. The address

bits (A5 – A0) sets the start address in an

internal address counter. This counter is

incremented by one each new byte (every 8

clock pulses). The burst access is either a

read or a write access and must be terminated

by setting CSn high.

For register addresses in the range 0x30-

0x3D, the burst bit is used to select between

status registers, burst bit is one, and command

strobes, burst bit is zero (see Section 10.4

below). Because of this, burst access is not

available for status registers and they must be

accessed one at a time. The status registers

can only be read.

10.3

SPI Read

When reading register fields over the SPI

interface while the register fields are updated

CC2550-RTY1 数据表(PDF) 16 Page - Texas Instruments

CC2550-RTY1 数据表(HTML) 16 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表下载