6.

3 eMMC Communication Interface

The eMMC device transfers data via a configurable number of data bus signals. The communication signals

are:



Clock (CLK)

Each cycle of this signal directs a one bit transfer on the command and either a one bit (1x) or a two

bits transfer (2x) on all the data lines. The frequency may vary between zero and the maximum clock

frequency.



Data Strobe (DS)

This signal is generated by the device and used for output in HS400 mode. The frequency of this signal

follows the frequency of CLK. For data output each cycle of this signal directs two bits transfer(2x) on

the data - one bit for positive edge and the other bit for negative edge. For CRC status response output

and CMD response output (enabled only HS400 enhanced strobe mode), the CRC status is latched on

the positive edge only, and don't care on the negative edge.



Command (CMD)

This signal is a bidirectional command channel used for Device initialization and transfer of

commands. The CMD signal has two operation modes: open-drain for initialization mode, and push-

pull for fast command transfer. Commands are sent from the eMMC host controller to the eMMC

Device and responses are sent from the Device to the host.



Input/Outputs (DAT0-DAT7)

These are bidirectional data channels. The DAT signals operate in push-pull mode. Only the Device or

the host is driving these signals at a time. By default, after power up or reset, only DAT0 is used for

data transfer. A wider data bus can be configured for data transfer, using either DAT0-DAT3 or DAT0-

DAT7, by the eMMC host controller. The eMMC Device includes internal pull-ups for data lines DAT1-

DAT7.

Immediately after entering the 4-bit mode, the Device disconnects the internal pull ups of lines DAT1,

DAT2, and DAT3. Correspondingly, immediately after entering to the 8-bit mode the Device disconnects

the internal pull-ups of lines DAT1–DAT7.

6.

4Bus Protocol

After a power-on reset, the host must initialize the device by a special message-based eMMC bus protocol.

For more details, refer to section 5.3.1 of the JEDEC Standard JESD84-B51.

6.

5Bus Speed Modes

eMMC defines several bus speed modes as shown in

following Table 15.

Table 15: Bus Speed Mode

Mode Name

Data Rate

IO Voltage

Bus Width

Frequency

Max Data Transfer

(implies x8 bus

width)

Backwards

Compatibility with

legacy MMC card

Single

3.3/1.8V

1, 4, 8

0-26MHz

26MB/s

High Speed SDR

Single

3.3/1.8V

4, 8

0-52MHz

52MB/s

High Speed DDR

Dual

3.3/1.8V

4, 8

0-52MHz

104MB/s

HS200

Single

1.8V

4, 8

0-200MHz

200MB/s

HS400

Dual

1.8V

8

0-200MHz

400MB/s

6.5.1 HS200 Bus Speed Mode



SDR Data sampling method



CLK frequency up to 200MHz Data rate – up to 200MB/s



8-bits bus width supported



Single ended signaling with 4 selectable Drive Strength



Signaling levels of 1.8V



Tuning concept for Read Operations

Confidential

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／42-

Rev.1.0 July 2023

The HS200 mode offers the following features:

32GB/64GB/128GB eMMC