6.5.2 HS200 System Block Diagram

Figure 6 shows a typical HS200 Host and Device system. The host has a clock generator, which supplies CLK to

the Device. For write operations, clock and data direction are the same, write data can be transferred

synchronous with CLK, regardless of transmission line delay. For read operations, clock and data direction are

opposite; the read data received by Host is delayed by round-trip delay, output delay and latency of Host and

Device. For reads, the Host needs to have an adjustable sampling point to reliably receive the incoming data.

Figure 6: HS200 Host and Device block diagram

The HS400 mode has the following features:

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DDR Data sampling method

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CLK frequency up to 200MHz, Data rate is – up to 400MB/s

•

Only 8-bit bus width supported

•

Signaling levels of 1.8V

•

Support up to 5 selective Drive Strength

•

Data strobe signal is toggled only for Data out and CRC response

Figure 7 shows a typical HS400 Host and Device system. The host has a clock generator, which supplies CLK to

the Device. For read operations, Data Strobe is generated by device output circuit. Host receives the data

which is aligned to the edge of Data Strobe.

Figure 7: HS400 Host and Device block diagram

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6.5.3 HS400 Bus Speed mode

6.5.4 HS400 System Block Diagram

32GB/64GB/128GB eMMC