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ASFC 数据表(PDF) 32 Page - Alliance Semiconductor Corporation |
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ASFC 数据表(HTML) 32 Page - Alliance Semiconductor Corporation |
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32 / 42 page ![]() 8.7 Bus Timing Specification in HS400 mode HS400 Device Input Timing The CMD input timing for HS400 mode is the same as CMD input timing for HS200 mode. Figure 22 and Table 30show Device input timing. Figure 22: HS400 Device Data input timing Table 30: HS400 Device input timing Parameter Symbol Min. Max. Unit Remark Input CLK Cycle time data transfer mode tPERIOD 5 200MHz(Max), between rising edges with respect to VT. Slew rate SR 1.125 V/ns With respect to VIH/VIL. Duty cycle distortion tCKDCD 0.0 0.3 ns Allowable deviation from an ideal 50% duty cycle. With respect to VT. Includes jitter, phase noise Minimum pulse width tCKMPW 2.2 ns With respect to VT. Input DAT (referenced to CLK) Input set-up time tISUddr 0.4 ns CDevice ≤ 6pF With respect to VIH/VIL. Input hold time tIHddr 0.4 ns CDevice ≤ 6pF With respect to VIH/VIL. Slew rate SR 1.125 V/ns With respect to VIH/VIL. Confidential -32 /42- Rev.1.0 July 2023 32GB/64GB/128GB eMMC |
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