eMMC Power Cycling

The master can execute any sequence of VCC and VCCQ power-up/power-down. However, the master must not

issue any commands until VCC and VCCQ are stable within each operating voltage range. After the slave enters

sleep mode, the master can power-down VCC to reduce power consumption. It is necessary for the slave to be

ramped up to VCC before the host issues CMD5 (SLEEP_AWAKE) to wake the slave unit. For more information

about power cycling refer to Section 10.1.3 of the JEDEC Standard JESD84-B51.

Figure 12: eMMC Power Cycle

8.2 Bus Operating Conditions

Table 17: General Operating Conditions

Parameter

Symbol

Min.

Max.

Unit

Remark

Peak voltage on all lines

-0.5

VCCQ +

0.5

V

All Inputs

Input Leakage Current (before initialization sequence and/or the

internal pull up resistors connected)

-100

100

μA

Input Leakage Current (after initialization sequence and the

internal pull up resistors disconnected)

-2

2

μA

All Outputs

Output Leakage Current (before initialization sequence)

-100

100

μA

Output Leakage Current (after initialization sequence)

-2

2

μA

Confidential

-20

／42-

Rev.1.0 July 2023

32GB/64GB/128GB eMMC