8.6 Bus Timing Specification in HS200 Mode

HS200 Clock Timing

Host CLK Timing in HS200 mode shall conform to the timing specified in Figure 18 and Table 27.

CLK input shall satisfy the clock timing over all possible operation and environment conditions. CLK input

parameters should be measured while CMD and DAT lines are stable high or low, as close as possible to the

Device.

The maximum frequency of HS200 is 200MHz. Hosts can use any frequency up to the maximum that HS200

mode allows.

Figure 18: HS200 Clock Signal Timing

Note 1: VIH denote VIH(min.) and VIL denotes VIL(max.).

Note 2: VT=0.975V – Clock Threshold, indicates clock reference point for timing measurements.

Table 27: HS200 Clock Signal Timing

Symbol

Min.

Max.

Unit

Remark

tPERIOD

5

-

ns

200MHz (Max.), between rising edges

tTLH, tTHL

-

0.2* tPERIOD

ns

tTLH, tTHL < 1ns (max.) at 200MHz, CBGA=12pF, The absolute

maximum value of tTLH, tTHL is 10ns regardless of clock frequency.

Duty Cycle

30

70

%

Confidential

-28

／42-

Rev.1.0 July 2023

32GB/64GB/128GB eMMC