Memory Addressing

Previous implementations of the eMMC specification (versions up to v4.1) implemented byte addressing using

a 32 bit field. This addressing mechanism permitted for eMMC densities up to and including 2 GB.

To support larger densities the addressing mechanism was update to support sector addresses (512 B sectors).

The sector addresses shall be used for all devices with capacity larger than 2 GB.

To determine the addressing mode use the host should read bit [30:29] in the OCR register.

9.2 CID Register

The Card Identification (CID) register is 128 bits wide. It contains the Device identification information used

during the Device identification phase (eMMC protocol). For details, refer to section 7.2 of the JEDEC Standard

JESD84-B51.

Table 35: CID register

Register Name

Bit Width

Description

typ. Value

MID

8

Manufacture ID

0x

52

—

6

Reserved

000000

CBX

2

Device/BGA

01

OID

8

OEM/Application ID

0x

52

PNM

48

Product Name 32GB

“

AS032G”

8

Product Revision for 32GB

0x11

PRV

PSN

32

Product Serial Number

xxxxxxxx

MDT

8

Manufacture Date

xx

CRC

7

Check sum of CID contents

CRC7 chksum

—

1

Not used; always=1

1

Product Name 64GB

“

AS064G”

Product Name 128GB

“

AS128G”

Product Revision for 64GB & 128GB

0x12

9.3 CSD Register

The Device-Specific Data (CSD) register provides information on how to access the Device contents. The CSD

defines the data format, error correction type, maximum data access time, data transfer speed, whether the

DSR register can be used etc. For details, refer to section 7.3 of the JEDEC Standard JESD84-B51.

Table 36: CSD register

Register Name

Bits

Bit Width Description

typ. Value

CSD_STRUCTURE

127:126

2

CSD structure

0x3

SPEC_VERS

125:122

4

System Specification version

0x4

—

121:120

2

Reserved

-

TAAC

119:112

8

Data read access-time 1

0x27

NSAC

111:104

8

Data read access-time 2 in CLK cycle

(NSAC*100)

0x01

TRAN_SPEED

103:96

8

Max. bus clock frequency

0x32

CCC

95:84

12

Device command classes

0x0F5 (32GB)

0x8F5

(64GB)

0x8F5 (128GB)

READ_BL_LEN

83:80

4

Max. read data block length

0x9

READ_BL_PARTIAL

79

1

Partial blocks for read allowed

0x0

Confidential

-35

／42-

Rev.1.0 July 2023

32GB/64GB/128GB eMMC