Table 25: Backward-compatible Device Interface Timing

Parameter

Symbol

Min.

Max.

Unit

Remark1

Clock CLK2

Clock frequency Data Transfer Mode

(PP)3

fPP

0

26

MHz

CL ≤ 30 pF

Clock frequency Identification Mode

(OD)

fOD

0

400

kHz

Clock high time

tWH

10

CL ≤ 30 pF

Clock low time

tWL

10

ns

CL ≤ 30 pF

Clock rise time4

tTLH

10

ns

CL ≤ 30 pF

Clock fall time

tTHL

10

ns

CL ≤ 30 pF

Inputs CMD, DAT (referenced to CLK)

Input set-up time

tISU

3

ns

CL ≤ 30 pF

Input hold time

tIH

3

ns

CL ≤ 30 pF

Outputs CMD, DAT (referenced to CLK)

Output set-up time5

tOSU

11.7

ns

CL ≤ 30 pF

Output hold time5

tOH

8.3

ns

CL ≤ 30 pF

Note 1: The Device must always start with the backward-compatible interface timing. The timing mode can be switched to high-speed

interface timing by the host sending the SWITCH command (CMD6) with the argument for high-speed interface select.

Note 2: CLK timing is measured at 50% of VDD.

Note 3: For compatibility with Devices that support the v4.2 standard or earlier, host should not use > 26 MHz before switching to high

speed interface timing.

Note 4: CLK rise and fall times are measured by min (VIH) and max (VIL).

Note 5: tOSU and tOH are defined as values from clock rising edge. However, there may be Devices or devices which utilize clock falling

edge to output data in backward compatibility mode. Therefore, it is recommended for hosts either to settWL value as long as

possible within the range which will not go over tCK-tOH(min) in the system or to use slow clock frequency, so that host could

have data set up margin for those devices. In this case, each device which utilizes clock falling edge might show the correlation

either between tWL and tOSU or between tCK and tOSU for the device in its own datasheet as a note or its application notes.

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