7.7 H/W Reset Operation

Figure 8: H/W Reset Waveform

1.

Device will detect the rising edge of RST_n signal to trigger internal reset sequence

Table 16: H/W Reset Timing Parameters

Symbol

Comment

Min.

Max.

Unit

tRSTW

RST_n pulse width

1

[us]

tRSCA

RST_n to Command time

2001

[us]

tRSTH

RST_n high period (interval time)

1

[us]

1.

74 cycles of clock signal required before issuing CMD1 or CMD0 with argument 0xFFFFFFFA

7.8 Noise Filtering Timing for H/W Reset

Device must filter out 5ns or less pulse width for noise immunity

Figure 9: Noise Filtering Timing for H/W Reset

Device must not detect these rising edge.

Device must not detect 5ns or less of positive or negative RST_n pulse. Device must detect more than or equal

to 1us of positive or negative RST_n pulse width.

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Rev.1.0 July 2023

32GB/64GB/128GB eMMC