AM263P4 datasheet(90/168 Pages) TI2

90 / 168 page

VDD, VDDARn (1.2 V)

1.2V Power Good

Output (PG_1V2)

VDDS33, VDDA33 (3.3 V)

3.3V Power Good

Output (PG_3V3)

PORz

tRamp_3V3

SOP[3:0]

tSOP_Sampled

PG_1V2 AND PG_3V3

tStartup

tPGood

tSU_SOP

tH_SOP

tPORz

WARMRSTn

tWARMRSTn

Pin is Tristate.

Signal Level determined by external pull or driver.

Figure 6-2. Power-On Sequencing

6.11.2.1.1 Power Reset Sequence Description

The following set of steps shall occur on the EVM and AM263Px to boot the device from power-on reset.

1. PORz is held low by the external power supply monitor

2. VDD core digital 1.2V and VDDS3V3/VDDA3V3 3.3V supplies ramp to their nominal voltages

a. This requires a logical AND be applied to the power good signal generated from each supply

3. SOP[3:0] pins held in their boot latch state

4. After PCB supplied power nets are stable, the external supply monitor will de-assert PORz

5. Device will startup 1.8V on-die LDO

6. After internal supply monitors show externally and internally generated supplies are stable, the SOP[3:0] pin

states are latched

7. R5F cores are unhalted and SOP selected boot ROM execution begins

AM263P4, AM263P2, AM263P4-Q1, AM263P2-Q1

SPRSP81D – OCTOBER 2023 – REVISED MAY 2025

www.ti.com

Submit Document Feedback

Product Folder Links: AM263P4 AM263P2 AM263P4-Q1 AM263P2-Q1

AM263P4 数据表(PDF) 90 Page - Texas Instruments

AM263P4 数据表(HTML) 90 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载