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AM263P4 数据表(PDF) 95 Page - Texas Instruments

部件名 AM263P4
功能描述  AM263Px Sitara™ Microcontrollers with Optional Flash-in-Package
PDF  168 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

AM263P4 数据表(HTML) 95 Page - Texas Instruments

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6.11.5 Peripherals
6.11.5.1 2-port Gigabit Ethernet MAC (CPSW)
Note
The CPSW supports two external Ethernet ports and one internal port.
For more details about features and additional description information on the device CPSW (2-port Gigabit
Ethernet MAC), see the corresponding subsections within Signal Descriptions and Detailed Description sections.
6.11.5.1.1 CPSW MDIO Timing
6.11.5.1.1.1 CPSW MDIO Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input Slew Rate
0.9
3.6
V/ns
OUTPUT CONDITIONS
CL
Output Load Capacitance
10
470
pF
6.11.5.1.1.2 CPSW MDIO Timing Requirements
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MDIO1
tsu(MDIO-MDC)
Setup time, MDIO_DATA valid before
MDIO_CLK high
90
ns
MDIO2
th(MDC-MDIO)
Hold time, MDIO_DATA valid after MDIO_CLK
high
0
ns
6.11.5.1.1.3 CPSW MDIO Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MDIO3
tc(MDC)
Cycle time, MDIO_CLK
400
ns
MDIO4
tw(MDCH)
Pulse duration, MDIO_CLK high
160
ns
MDIO5
tw(MDCL)
Pulse duration, MDIO_CLK low
160
ns
MDIO7
td(MDC_MDIO)
Delay time, MDIO_CLK low to MDIO_DATA
valid
–150
150
ns
MDIO3
MDIO1
MDIO2
MDIO7
MDIO4
MDIO5
MDIO[x]_MDC
MDIO[x]_MDIO
(input)
MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01
Figure 6-8. CPSW MDIO Timing Requirements and Switching Characteristics
www.ti.com
AM263P4, AM263P2, AM263P4-Q1, AM263P2-Q1
SPRSP81D – OCTOBER 2023 – REVISED MAY 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: AM263P4 AM263P2 AM263P4-Q1 AM263P2-Q1



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