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BQ40Z50-R2 数据表(PDF) 43 Page - Texas Instruments |
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BQ40Z50-R2 数据表(HTML) 43 Page - Texas Instruments |
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43 / 55 page ![]() Current Direction To SRP – SRN pin or HSRP – HSRN pin RSNS Current Sensing Direction Figure 11-3. Sensing Resistor PCB Layout Sense Resistor Ground Shield Filter Circuit Figure 11-4. Sense Resistor, Ground Shield, and Filter Circuit Layout 11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors Use wide copper traces to lower the inductance of the bypass capacitor circuit. Figure 11-5 shows an example layout, demonstrating this technique. Copyright © 2016, Texas Instruments Incorporated Pack+ C2 C3 F1 Pack± C1 BAT+ BAT± Low Level Circuits C1 J1 R1 F1 Q2 C2 Q1 C3 J1 Figure 11-5. Use Wide Copper Traces to Lower the Inductance of Bypass Capacitors C1, C2, and C3 11.1.2 ESD Spark Gap Protect SMBus clock, data, and other communication lines from ESD with a spark gap at the connector. The pattern in Figure 11-6 is recommended, with 0.2-mm spacing between the points. www.ti.com BQ40Z50-R2 SLUSCS4C – JUNE 2017 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: BQ40Z50-R2 |
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