BQ40Z50-R2 datasheet(13/55 Pages) TI2

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7.16 ADC (continued)

Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Integral nonlinearity(1)

16-bit, best fit, –0.1 V to 0.8 × VREF1

±6.6

LSB

16-bit, best fit, –0.2 V to –0.1 V

±13.1

Offset error(2)

16-bit, Post-calibration, VFS = VREF1

±67

±157

µV

Offset error drift

16-bit, Post-calibration, VFS = VREF1

0.6

µV/°C

Gain error

16-bit, –0.1 V to 0.8 × VFS

±0.2%

±0.8%

FSR

Gain error drift

16-bit, –0.1 V to 0.8 × VFS

150

PPM/°C

Effective input resistance

MΩ

(1)

1 LSB = VREF1/(2N) = 1.225/(215) = 37.4 µV (when tCONV = 31.25 ms)

(2)

For VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC4–VSS, PACK–VSS, and VREF1/2, the offset error is multiplied by (1/ADC

multiplexer scaling factor (K)).

7.17 ADC Digital Filter

Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Conversion time

Single conversion

31.25

Single conversion

15.63

Single conversion

7.81

Single conversion

1.95

Resolution

No missing codes

Bits

Effective resolution

With sign, tCONV = 31.25 ms

Bits

With sign, tCONV = 15.63 ms

With sign, tCONV = 7.81 ms

With sign, tCONV = 1.95 ms

7.18 CHG, DSG FET Drive

Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Output voltage

ratio

RatioDSG = (VDSG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V, 10

MΩ between PACK and DSG

2.133

2.333

2.433

—

RatioCHG = (VCHG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V, 10

MΩ between BAT and CHG

2.133

2.333

2.433

V(FETON)

Output voltage,

CHG and DSG on

VDSG(ON) = VDSG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between

PACK and DSG, VBAT = 18 V

10.5

11.5

VCHG(ON) = VCHG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between

BAT and CHG, VBAT = 18 V

10.5

11.5

V(FETOFF)

Output voltage,

CHG and DSG off

VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and

DSG

–0.4

0.4

VCHG(OFF) = VCHG – VBAT, 10 MΩ between BAT and CHG

–0.4

0.4

Rise time

VDSG from 0% to 35% VDSG (ON)(TYP), VBAT ≥ 2.2 V, CL =

4.7 nF between DSG and PACK, 5.1 kΩ between DSG

and CL, 10 MΩ between PACK and DSG

200

500

µs

VCHG from 0% to 35% VCHG (ON)(TYP), VBAT ≥ 2.2 V, CL =

4.7 nF between CHG and BAT, 5.1 kΩ between CHG and

CL, 10 MΩ between BAT and CHG

200

500

www.ti.com

BQ40Z50-R2

SLUSCS4C – JUNE 2017 – REVISED APRIL 2021

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