ADE7166 datasheet(46/144 Pages) AD

46 / 144 page

ADE7566/ADE7569/ADE7166/ADE7169

Rev. A | Page 46 of 144

Table 44. Interrupt Enable 3 SFR (MIRQENH, 0xDB)

Bit

Interrupt Enable Bit

Description

7 to 6

Reserved.

WFSM

When this bit is set, the WFSM flag set creates a pending ADE interrupt to the 8052 core.

PKI

When this bit is set, the PKI flag set creates a pending ADE interrupt to the 8052 core.

PKV

When this bit is set, the PKV flag set creates a pending ADE interrupt to the 8052 core.

CYCEND

When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.

ZXTO

When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.

When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core.

K × VIN

VP1

VN1

000

0000

7654

3210

GAIN[7:0]

GAIN (K)

SELECTION

VIN

ANALOG INPUTS

Each ADE7566/ADE7569/ADE7166/ADE7169 has two fully

differential voltage input channels. The maximum differential

input voltage for input pairs VP/VN and IP/IN is ±0.4 V. for the

ADE7566 and ADE7569.

For the ADE7166 and ADE7169, PGA1 = 1 is not recommended

because at full scale, when both IPA and IPB are 180° out of phase,

the ADC can be overranged. It is recommended, for these

products, that PGA1 = 2, 4, 8, or 16 be used.

Each analog input channel has a programmable gain amplifier

(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The

gain selections are made by writing to the GAIN register (see

Figure 40. PGA in Current Channel

000

654

GAIN REGISTER*

CURRENT AND VOLTAGE CHANNELS PGA CONTROL

PGA2 GAIN SELECT

000 = × 1

001 = × 2

010 = × 4

011 = × 8

100 = × 16

PGA1 GAIN SELECT

000 = × 1

001 = × 2

010 = × 4

011 = × 8

100 = × 16

RESERVED

*REGISTER CONTENTS SHOW POWER-ON DEFAULTS.

ADDR:

0x1B

CFSIGN_OPT

Table 37 and Figure 41). Bit 0 to Bit 2 select the gain for the PGA

in the current channel, and Bit 5 to Bit 7 select the gain for the

PGA in the voltage channel. For the ADE7166 and ADE7169, it

is recommended that PGA1 = 2, 4, 8, or 16 be used. Figure 40

shows how a gain selection for the current channel is made

using the gain register.

Figure 41. Analog Gain Register

ADE7166 数据表(PDF) 46 Page - Analog Devices

ADE7166 数据表(HTML) 46 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载