ADE7166 datasheet(78/144 Pages) AD

78 / 144 page

ADE7566/ADE7569/ADE7166/ADE7169

Rev. A | Page 78 of 144

8052 MCU CORE ARCHITECTURE

ENERGY

MEASUREMENT

16kB ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE

PROGRAM/DATA

MEMORY

8051

COMPATIBLE

CORE

256 BYTES XRAM

OTHER ON-CHIP

PERIPHERALS:

• SERIAL I/O

• WDT

• TIMERS

BATTERY

ADC

LCD DRIVER

TEMPERATURE

ADC

RTC

POWER

MANAGEMENT

128-BYTE

SPECIAL

FUNCTION

AREA

STACK

256 BYTES

GENERAL

PURPOSE

RAM

BANKS

The ADE7566/ADE7569/ADE7166/ADE7169 have an 8052

MCU core and use the 8052 instruction set. Some of the

standard 8052 peripherals, such as the UART, have been

enhanced. This section describes the standard 8052 core and its

enhancements used in the ADE7566/ADE7569/ADE7166/

ADE7169.

The special function register (SFR) space is mapped into the

upper 128 bytes of internal data memory space and is accessed

by direct addressing only. It provides an interface between the

CPU and all on-chip peripherals. A block diagram showing the

programming model of the ADE7566/ADE7569/ADE7166/

ADE7169 via the SFR area is shown in Figure 80.

Figure 80. ADE7566/ADE7569/ADE7166/ADE7169 Block Diagram

All registers except the program counter (PC), instruction

reside in the SFR area. The SFR registers include power

control, configuration, and data registers that provide an

interface between the CPU and all on-chip peripherals.

MCU REGISTERS

The registers used by the MCU are summarized in this section.

Table 55. 8052 SFRs

Address

Mnemonic

Bit Addressable

Description

0xE0

ACC

Yes

Accumulator.

0xF0

Yes

Auxiliary Math Register.

0xD0

PSW

Yes

Program Status Word (see Table 56).

0x87

PCON

Program Control Register (see Table 57).

0x82

DPL

Data Pointer Low (see Table 58).

0x83

DPH

Data Pointer High (see Table 59).

0x83 and 0x82

DPTR

Data Pointer (see Table 60).

0x81

Stack Pointer (see Table 61).

0xAF

CFG

Configuration (see Table 62).

Table 56. Program Status Word SFR (PSW, 0xD0)

Bit

Address

Mnemonic

Description

0xD7

Carry Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.

0xD6

Auxiliary Carry Flag. Modified by ADD and ADDC instructions.

0xD5

General-Purpose Flag Available to the User.

4 to 3

0xD4, 0xD3

RS1, RS0

RS1

RS0

Result (Selected Bank)

0xD2

Overflow Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.

0xD1

General-Purpose Flag Available to the User.

0xD0

Parity Bit. The number of bits set in the accumulator added to the value of the parity bit is always an

even number.

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