ADE7166 datasheet(50/144 Pages) AD

50 / 144 page

ADE7566/ADE7569/ADE7166/ADE7169

Rev. A | Page 50 of 144

Voltage Channel ADC

Figure 47 shows the ADC and signal processing chain for the

voltage channel. In waveform sampling mode, the ADC outputs

a signed, twos complement, 24-bit data-word at a maximum

of 25.6 kSPS (MCLK/160). The ADC produces an output code

that is approximately between 0x28F5 (+10,485d) and 0xD70B

(−10,485d).

Channel Sampling

The waveform samples of the current ADC and voltage ADC

can also be routed to the waveform registers to be read by the

MCU core. The active, reactive, apparent power, and energy

calculation remain uninterrupted during waveform sampling.

When in waveform sampling mode, one of four output sample

rates can be chosen by using the DTRT[1:0] bits of the WAVMODE

12.8 kSPS, 6.4 kSPS, or 3.2 kSPS. If the WFSM enable bit is set

in the Interrupt Enable 3 SFR (MIRQENH, 0xDB), the 8052

core has a pending ADE interrupt. The sampled signals selected

in the WAVMODE register are latched into the Waveform SFRs

when the waveform high byte (WAV1H or WAV2H) is read.

The ADE interrupt stays active until the WFSM status bit is

cleared (see the Energy Measurement Interrupts section).

FAULT DETECTION1

The ADE7166/ADE7169 incorporate a fault detection scheme

that warns of fault conditions and allows the ADE7166/ADE7169

to continue accurate measurement during a fault event. The

ADE7166/ADE7169 do this by continuously monitoring both

current inputs (IPA and IPB). For ease of understanding, these

currents are referred to as phase and neutral (return) currents.

In the ADE7166/ADE7169, a fault condition is defined when

the difference between IPA and IPB is greater than 6.25% of the

active channel. If a fault condition is detected and the inactive

channel is larger than the active channel, the

ADE7166/ADE7169 automatically switch current measurement to

the inactive channel. During a fault, the active, reactive, current

rms and apparent powers are generated using the larger of the

two currents. On power-up, IPA is the current input selected for

active, reactive, and apparent power and Irms calculations.

To prevent false alarm, averaging is done for the fault detection,

and a fault condition is detected approximately one second after

the event. The fault detection is automatically disabled when the

voltage signal is less than 0.3% of the full-scale input range. This

eliminates false detection of a fault due to noise at light loads.

Because the ADE7166/ADE7169 look for a difference between

the voltage signals on IPA and IPB, it is important that both

current transducers be closely matched.

Channel Selection Indication

The current channel selected for measurement is indicated by

Bit 7 (ICHANNEL) in the ACCMODE Register (0x0F). When

this bit is cleared, IPA is selected and, when it is set, IPB is

selected. The ADE7166/ADE7169 automatically switch from

one channel to the other and report the channel configuration

in the

1 This function is not available in the ADE7566 and ADE7569.

ACCMODE Register (0x0F).

The current channel selected for measurement can also be

forced. Setting the SEL_I_CH[1:0] bits in the CALMODE

are cleared or set, the current channel used for measurement is

selected automatically based on the fault detection.

Fault Indication

The ADE7166/ADE7169 provide an indication of the part going

in or out of a fault condition. The new fault condition is

indicated by the FAULTSIGN flag (Bit 5) in the Interrupt Status

1 SFR (MIRQSTL, 0xDC).

When FAULTSIGN bit (Bit 6) of the ACCMODE Register

(0x0F) is cleared, the FAULTSIGN flag in the Interrupt Status 1

SFR (MIRQSTL, 0xDC) is set when the part is a entering fault

condition or a normal condition.

When the FAULTSIGN bit is set in the Interrupt Enable 1 SFR

(MIRQENL, 0xD9), and the FAULTSIGN flag in the Interrupt

Status 1 SFR (MIRQSTL, 0xDC) is set, the 8052 core has a

pending ADE interrupt.

Fault with Active Input Greater Than Inactive Input

If IPA is the active current input (that is, being used for billing),

and the voltage signal on IPB (inactive input) falls below 93.75%

of IPA, and the FAULTSIGN bit (Bit 6) of ACCMODE Register

(0x0F) is cleared, the FAULTSIGN flag in the Interrupt Status 1

SFR (MIRQSTL, 0xDC) is set. Both analog inputs are filtered

and averaged to prevent false triggering of this logic output. As

a consequence of the filtering, there is a time delay of

approximately three seconds on the logic output after the fault

event. The FAULTSIGN flag is independent of any activity.

Because IPA is the active input and it is still greater than IPB,

billing is maintained on IPA; that is, no swap to the IPB input

occurs. IPA remains the active input.

Fault with Inactive Input Greater Than Active Input

If the difference between IPB, the inactive input, and IPA, the

active input (that is, being used for billing), becomes greater

than 6.25% of IPB, and the FAULTSIGN bit (Bit 6) of ACCMODE

Status 1 SFR (MIRQSTL, 0xDC) is set. The analog input IPB

becomes the active input. Again, a time constant of about three

seconds is associated with this swap. IPA does not swap back to

the active channel until IPA is greater than IPB and the difference

between IPA and IPB—in this order—becomes greater than 6.25%

of IPB. However, if FAULTSIGN bit (Bit 6) of ACCMODE

Status 1 SFR (MIRQSTL, 0xDC) is set as soon as IPA is within

6.25% of IPB. This threshold eliminates potential chatter

between IPA and IPB.

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