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ADE7166 数据表(PDF) 95 Page - Analog Devices

部件名 ADE7166
功能描述  Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
PDF  144 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7166 数据表(HTML) 95 Page - Analog Devices

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ADE7566/ADE7569/ADE7166/ADE7169
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Table 76. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA)
Bit
Mnemonic
Default
Description
This bit holds the protection for the watchdog timer and the 7th bit of the flash protection key.
When this bit is cleared, the watchdog enable and event bits WDE and WDIR cannot be changed
by user code. The watchdog configuration is then fixed to WDIR = 0 and WDE = 1. The watchdog
timeout in PRE[3:0] can still be modified by user code.
7
WDPROT_PROTKY7
1
The value of this bit is also used to set the flash protection key. If this bit is cleared to protect the
watchdog, then the default value for the flash protection key is 0x7F instead of 0xFF (see the
Protecting the Flash Memory section for more information on how to clear this bit).
6 to 0
PROTKY[7:0]
0xFF
These bits hold the flash protection key. The content of this flash address is compared to the
Flash Protection Key SFR (PROTKY, 0xBB) when the protection is being set or changed. If the two
values match, the new protection is written to the flash Address 0x3FFF to Address 0x3FFB. See
the Protecting the Flash Memory section for more information on how to configure these bits.
Writing to the Watchdog Timer SFR (WDCON, 0xC0)
Writing data to the WDCON SFR involves a double instruction
sequence. The WDWR bit must be set and the following
instruction must be a write instruction to the WDCON SFR.
Disable Watch dog
CLR EA
SETB WDWR
CLR WDE
SETB EA
This sequence is necessary to protect the WDCON SFR from
code execution upsets that may unintentionally modify this
SFR. Interrupts should be disabled during this operation due to
the consecutive instruction cycles.
Watchdog Timer Interrupt
If the watchdog timer is not cleared within the watchdog timeout
period, a system reset occurs unless the watchdog timer interrupt
is enabled. The watchdog timer interrupt enable bit (WDIR) is
located in the Watchdog Timer SFR (WDCON, 0xC0). Enabling
the WDIR bit allows the program to examine the stack or other
variables that may have led the program to execute inappropriate
code. The watchdog timer interrupt also allows the watchdog to
be used as a long interval timer.
Note that WDIR is automatically configured as a high priority
interrupt. This interrupt cannot be disabled by the EA bit in the
IE register (see Table 68). Even if all of the other interrupts are
disabled, the watchdog is kept active to watch over the program.



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