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ADE7166 数据表(PDF) 74 Page - Analog Devices |
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ADE7166 数据表(HTML) 74 Page - Analog Devices |
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74 / 144 page  ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 74 of 144 Table 49. Temperature and Supply Delta SFR (DIFFPROG, 0xF3) Bit Mnemonic Default Description 7 to 6 Reserved 0 Reserved. Difference threshold between last temperature measurement interrupting 8052 and new temperature measurement that should interrupt 8052. TEMP_DIFF[2:0] Result 000 No interrupt 001 1 LSB (≈ 0.8°C) 010 2 LSB (≈ 1.6°C) 011 3 LSB (≈ 2.4°C) 100 4 LSB (≈ 3.2°C) 101 5 LSB (≈ 4°C) 110 6 LSB (≈ 4.8°C) 5 to 3 TEMP_DIFF[2:0] 0 111 Every temperature measurement Difference threshold between last external voltage measurement interrupting 8052 and new external measurement that should interrupt 8052. VDCIN_DIFF[2:0] Result 000 No interrupt 001 1 LSB (≈ 120 mV) 010 2 LSB (≈ 240 mV) 011 3 LSB (≈ 360 mV) 100 4 LSB (≈ 480 mV) 101 5 LSB (≈ 600 mV) 110 6 LSB (≈ 720 mV) 2 to 0 VDCIN_DIFF[2:0] 0 111 Every VDCIN measurement Table 50. Start ADC Measurement SFR (ADCGO, 0xD8) Bit Address Mnemonic Default Description 7 0xDF PLLACK 0 Set this bit to clear the PLL fault bit, PLL_FLT, in the PERIPH register. A PLL fault is generated if a reset is caused because the PLL lost lock. 6 to 3 0xDE to 0xDB Reserved 0 Reserved. 2 0xDA VDCIN_ADC_G O 0 Set this bit to initiate an external voltage measurement. This bit is cleared when the measurement request is received by the ADC. 1 0xD9 TEMP_ADC_GO 0 Set this bit to initiate a temperature measurement. This bit is cleared when the measurement request is received by the ADC. 0 0xD8 BATT_ADC_GO 0 Set this bit to initiate a battery measurement. This bit is cleared when the measurement request is received by the ADC. Table 51. Battery Detection Threshold SFR (BATVTH, 0xFA) Bit Mnemonic Default Description 7 to 0 BATVTH 0 The battery ADC value is compared to this register, the battery threshold register. If BATADC is lower than the threshold, an interrupt is generated. Table 52. VDCIN ADC Value SFR (VDCINADC, 0xEF) Bit Mnemonic Default Description 7 to 0 VDCINADC 0 The VDCIN ADC value in this register is updated when an ADC interrupt occurs. Table 53. Battery ADC Value SFR (BATADC, 0xDF) Bit Mnemonic Default Description 7 to 0 BATADC 0 The battery ADC value in this register is updated when an ADC interrupt occurs. Table 54. Temperature ADC Value SFR (TEMPADC, 0xD7) Bit Mnemonic Default Description 7 to 0 TEMPADC 0 The temperature ADC value in this register is updated when an ADC interrupt occurs. |
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