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ADE7166 数据表(PDF) 96 Page - Analog Devices |
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ADE7166 数据表(HTML) 96 Page - Analog Devices |
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96 / 144 page  ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 96 of 144 LCD DRIVER Using shared pins, the LCD module is capable of directly driving an LCD panel of 17 × 4 segments without compromising any ADE7566/ADE7569/ADE7166/ADE7169 functions. It is capable of driving LCDs with 2×, 3×, and 4× multiplexing. The LCD waveform voltages generated through internal charge pump circuitry support up to 5 V LCDs. An external resistor ladder for LCD waveform voltage generation is also supported. Each ADE7566/ADE7569/ADE7166/ADE7169 has an embedded LCD control circuit, driver, and power supply circuit. The LCD module is functional in all operating modes (see the Operating Modes section). LCD REGISTERS There are six LCD control registers that configure the driver for the specific type of LCD in the end system and set up the user display preferences. The LCD Configuration SFR (LCDCON, 0x95), LCD Configuration X SFR (LCDCONX, 0x9C), and LCD Configuration Y SFR (LCDCONY, 0xB1) contain general LCD driver configuration information including the LCD enable and reset, as well as the method of LCD voltage generation and multiplex level. The LCD Clock SFR (LCDCLK, 0x96) configures timing settings for LCD frame rate and blink rate. LCD pins are configured for LCD functionality in the LCD Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). Table 77. LCD Driver SFRs SFR Address R/W Name Description 0x95 R/W LCDCON LCD Configuration SFR (see Table 78). 0x96 R/W LCDCLK LCD Clock (see Table 82). 0x97 R/W LCDSEGE LCD Segment Enable (see Table 85). 0x9C R/W LCDCONX LCD Configuration X (see Table 79). 0xAC R/W LCDPTR LCD Pointer (see Table 86). 0xAE R/W LCDDAT LCD Data (see Table 87). 0xB1 R/W LCDCONY LCD Configuration Y (see Table 81). 0xED R/W LCDSEGE2 LCD Segment Enable 2 (see Table 88). Table 78. LCD Configuration SFR (LCDCON, 0x95) Bit Mnemonic Value Description 7 LCDEN 0 LCD Enable. If this bit is set, the LCD driver is enabled. 6 LCDRST 0 LCD Data Registers Reset. If this bit is set, the LCD data registers are reset to zero. 5 BLINKEN 0 Blink Mode Enable Bit. If this bit is set, blink mode is enabled. The blink mode is configured by the BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96). Forces LCD off when in PSM2 (Sleep Mode). Note that the internal voltage reference must be enabled by setting the REF_BAT_EN bit in the Peripheral Configuration SFR (PERIPH, 0xF4) to allow LCD operation in PSM2. LCDPSM2 Result 0 The LCD is disabled or enabled in PSM2 by the LCDEN bit. 4 LCDPSM2 0 1 The LCD is disabled in PSM2 regardless of LCDEN setting. LCD Clock Selection. CLKSEL Result 0 fLCDCLK = 2048 Hz 3 CLKSEL 0 1 fLCDCLK = 128 Hz Bias Mode. BIAS Result 0 1/2 2 BIAS 0 1 1/3 LCD Multiplex Level. LMUX[1:0] Result 00 Reserved. 01 2× Multiplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as FP28. 10 3× Mulitplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as COM2. 1 to 0 LMUX[1:0] 0 11 4× Multiplexing. FP27/COM3 is used as COM3. FP28/COM2 is used as COM2. |
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