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ADE7166 数据表(PDF) 29 Page - Analog Devices |
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ADE7166 数据表(HTML) 29 Page - Analog Devices |
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29 / 144 page  ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 29 of 144 The Power Management Interrupt Enable SFR (IPSME, 0xEC) controls the events that result in a PSM interrupt (see POWER SUPPLY MONITOR INTERRUPT (PSM) Table 20). The power supply monitor interrupt (PSM) alerts the 8052 core of power supply events. The PSM interrupt is disabled by default. Setting the EPSM bit in the Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9) enables the PSM interrupt (see Figure 32 is a diagram illustrating how the PSM interrupt vector is shared among the PSM interrupt sources. The PSM interrupt flags are latched and must be cleared by writing to the IPSMF flag register (see Table 70). Table 17). EPSR FPSR ESAG FSAG EVADC FVADC EBAT FBAT EBSO FBSO EVDCIN FVDCIN FPSM EPSM TRUE? PENDING PSM INTERRUPT EPSR RESERVED ESAG RESERVED EVADC EBAT EBSO EVDCIN FPSR FPSM FSAG RESERVED FVADC FBAT FBSO FVDCIN RESERVED PTI RESERVED PSI EADE ETI EPSM ESI IPSME ADDR. 0xEC IPSMF ADDR. 0xF8 IEIP2 ADDR. 0xA9 NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN Figure 32. PSM Interrupt Sources |
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