ADE7166 datasheet(119/144 Pages) AD

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ADE7566/ADE7569/ADE7166/ADE7169

Rev. A | Page 119 of 144

READ AND WRITE OPERATIONS

Writing to the RTC Registers

The RTC circuitry runs off a 32.768 kHz clock. The timekeeping

registers, Hundredths of a Second Counter SFR (HTHSEC, 0xA2),

Seconds Counter SFR (SEC, 0xA3), Minutes Counter SFR (MIN,

0xA4), and Hours Counter SFR (HOUR, 0xA5), are updated

with a 32.768 kHz clock. However, the RTC Configuration SFR

(TIMECON, 0xA1) and Alarm Interval SFR (INTVAL, 0xA6)

are updated with a 128 Hz clock. It takes up to two 128 Hz clock

cycles from when the MCU writes to the TIMECON SFR or

INTVAL SFR until there is a successful update in the RTC.

To protect the RTC timekeeping registers from runaway code, a

key must be written to the Key SFR (KYREG, 0xC1), which is

described in Table 116, to obtain write access to the HTHSEC,

SEC, MIN and HOUR SFRs. KYREG should be set to 0xEA to

unlock the timekeeping registers and reset to 0 after a timekeeping

the following 8052 assembly code:

MOV

RTCKey,#0EAh

CALL

UpdateRTC

…

UpdateRTC:

MOV

KYREG,RTCKey

MOV

SEC,#30

MOV

KYREG,RTCKey

MOV

MIN,#05

MOV

KYREG,RTCKey

MOV

HOUR,#04

MOV

KYREG,#00h

RET

Reading the RTC Counter SFRs

The RTC cannot be stopped to read the current time because

stopping the RTC introduces an error in its timekeeping.

Therefore, the RTC is read on the fly, and the counter registers

must be checked for overflow. This can be accomplished

through the following 8052 assembly code:

ReadAgain:

MOV

R0,HTHSEC

; using Bank 0

MOV

R1,SEC

MOV

R2,MIN

MOV

R3,HOUR

MOV

A,HTHSEC

CJNE A, 00h, ReadAgain ; 00h is R0 in

Bank 0

RTC MODES

The RTC can be configured in a 24-hour mode or a 256-hour

mode. A midnight event is generated when the RTC hour

counter rolls over from 23 to 0 or 255 to 0, depending on

whether the TFH bit is set in the RTC Configuration SFR

(TIMECON, 0xA1). The midnight event sets the MIDNIGHT

flag in the TIMECON SFR, and a pending RTC interrupt is

created. The RTC midnight event wakes the 8052 MCU core if

the MCU is asleep in PSM2 when the midnight event occurs.

In the 24-hour mode, the midnight event is generated once a

day at midnight. The 24-hour mode is useful for updating a

software calendar to keep track of the current day. The 256-hour

mode results in power savings during extended operation in

PSM2 because the MCU core wakes up less frequently.

RTC INTERRUPTS

The RTC midnight interrupt and alarm interrupt are enabled by

setting the ETI bit in the Interrupt Enable and Priority 2 SFR

(IEIP2, 0xA9). When a midnight or alarm event occurs, a

pending RTC interrupt is generated. If the RTC interrupt is

enabled, the program vectors to the RTC interrupt address and

the pending interrupt is cleared. If the RTC interrupt is

disabled, the RTC interrupt remains pending until the RTC

interrupt is enabled. The program then vectors to the RTC

interrupt address.

The MIDNIGHT flag and ALARM flag are set when the

midnight event and alarm event occur, respectively. The user

should manage these flags to keep track of which event caused

an RTC interrupt by servicing the event and clearing the

appropriate flag in the RTC interrupt servicing routine.

Note that if the ADE7566/ADE7569/ADE7166/ADE7169 are

awakened by an RTC event, either by the MIDNIGHT event or

ALARM event, the pending RTC interrupt must be serviced

before the device can go back to sleep again. The ADE7566/

ADE7569/ADE7166/ADE7169 keep waking up until this

interrupt has been serviced.

Interval Timer Alarm

The RTC can be used as an interval timer. When the interval

timer is enabled by setting the ITEN bit in the RTC Configuration

SFR (TIMECON, 0xA1), the interval timer clock source selected

by the ITS1 and ITS0 bits is passed through an 8-bit counter.

This counter increments on every interval timer clock pulse

until it is equal to the value in the Alarm Interval SFR (INTVAL,

0xA6). Then, an alarm event is generated, setting the ALARM

flag and creating a pending RTC interrupt. If the SIT bit in the

RTC Configuration SFR (TIMECON, 0xA1) is cleared, the 8-bit

counter is also cleared and starts counting again. If the SIT bit is

set, the 8-bit counter is held in reset after the alarm occurs.

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