PROGRAMMABLE FILTER CHARACTERISTICS(continued)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

EOUT

Output Noise Voltage

Differentiated Output

BW = 100MHz, Rs = 50

Ω

FC = 18MHz, DACS = 0

–

2

7

mVrms

Output Noise Voltage Normal

Output

–

1.2

5

mVrms

Output Noise Voltage

Differentiated Output

BW = 100MHz, Rs = 50

Ω

FC = 18MHz, DACS = 127

–

4.6

7

mVrms

Output Noise Voltage Normal

Output

–

2

5

mVrms

IO-

Filter Output Sink Current

0.5

–

–

mA

IO+

Filter Output Source Current

2.0

–

–

mA

RO

Filter Output resistance Single

Ended

–

–

200

Ω

Note: FBDAC is value of boost DAC (i.e., no boost)

Filter Control Characteristics (RX = 12K

Ω)

VRX

Reference Current Set Output

Voltage

°C

(**)

–

1.5

–

V

FREQUENCY SYNTHESIZER CHARACTERISTICS (RR = 39K

Ω)

FIN

Input Frequency

8

20

MHz

FOUT

Output Frequency

–

96

MHz

JFO

FOUT jitter

TO = 1/FO; Fout = 30MHz

–

±400

ps(pk)

M Divide Number

80

255

–

N Divide Number

25

127

–

TVCO

VCO Center Frequency Period

-1

FLTR1-FLTR1 = 0 (***)

0.9TO

1.1TO

ns

VCO Frequency Dynamic

Range

–1.5

≤ FLTR1-FLTR1 ≤ +1.5,

Fout = 54.0MHz (***)

25

±45

%

KVCO

VCO Control Gain

ω =2π/TVCO

–1.5

≤ FLTR1-FLTR1 ≤ +1.5

0.14

0.26

KD

Phase Detector Gain

0.83KD

1.17KD

µA/rad

KVCO x KD Product Accuracy

– 28

+ 28

%

Reference Clock Characteristics:

Reference Clock Low Time

20

–

ns

Reference Clock High Time

20

–

ns

DATA SEPARATOR DYNAMIC CHARACTERISTICS AND TIMING (Unless otherwise specified, rec-

ommended operating conditions apply.)

Real Mode

TRRC

Read Clock Rise Time

0.8V to 2.0V, CL

≤ 15pF

–

8

ns

TFRC

Read Clock Fall time

2.0V to 0.8V, CL

≤ 15pF

–

5

ns

RRC Duty Cycle

DR = 32Mbit/s

43

57

%

TNS, TNH

NRZ(out) Set Up and Hold Time

DR

≤ 20Mbit/s (**)

15.5

–

ns

DR > 20Mbit/s (**)

13

–

ns

TPNRZ

NRZ (out) Propagation Delay

(**)

–

±15

ns

(**) Bench test only.

(***) Preliminary data.

L6000

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