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L6000 数据表(PDF) 13 Page - STMicroelectronics |
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L6000 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 24 page ![]() DATA SEPARATOR DYNAMIC CHARACTERISTICS AND TIMING (Continued) Symbol Parameter Test Condition Min. Typ. Max. Unit TAS, TAH AMD Set Up and Hold Time (**) 13 – ns TPAMD AMD Propagation Delay (**) – ±15 ns TD 1/3 Cell Delay TD = 1/FSOUT,RR = 39K Ω (***) 0.8TD 1.2TD ns Write Mode TWD Write Data Pulse Width 1.5V 2TFout/3 2TFout/3 ns CL ≤ 15pF – 5 + 5 TRWD Write Data Rise Time 0.8V to 2.0V, CL ≤ 15pF – 9 ns TFWD Write Data Fall Time 2.0V to 0.8V, CL ≤ 15pF – 5 ns TRWC Write Data Clock Rise Time 0.8V to 2.0V, CL ≤ 15pF – 10 ns TFWC Write Data Clock Fall Time 2.0V to 0.8V, CL ≤ 15pF – 8 ns TSNRZ NRZ Set Up Time 5 – ns THNRZ NRZ Hold Time 5 – ns TPC Precompensation Time Shift Magnitude Accuracy TPCO = 0.04TREF TPC(max) = 0.28TREF TPC = nTPCO n =0 1 ≤ n ≤ 7 – 0.5 n(0.8TPCO) – 0.5 + 0.5 n(1.2TPCO) +0.5 ns ns Data Synchronization TVCO VCO Center Frequency Period FLTR2-FLTR2 = 0 TO = (8.95 + 0.786 x DR) -1, RR = 39k Ω (***) 0.9TO 1.1TO ns VCO Frequency Dynamic range –1.5 ≤ FLTR-FLTR2 ≤ +1.5 (***) ±25 ±45 % KVCO VCO Control Gain ωo= 2 Π TVCO 0.14Wo 0.26Wo rad/(Vxs) –1.5 ≤ FLTR-FLTR2 ≤ +1.5 KD Phase Detector Gain Read: KD = 0.7 + 0.43 x DR, PLL REF = RD 3T Pattern, Non- Read: KD = 0.7 + 0.43 x DR, PLLREF = Fout / 2 (***) 0.83KD 1.17KD A/rad KVCO x KD Product Accuracy – 28 + 28 % VCO Phase Restart Error – 4 ns Decode Window Cent. Accuracy – ±1.5 ns Decode Window Width 2TORC/3 - 1.5 –ns SERIAL PORT TIMING Symbol Parameter Test Condition Min. Typ. Max. Unit Tc SERIAL CLOCK+ Data Clock Period 100 – ns Tck1 SERIAL CLOCK+ Low Time 40 – ns TcKh SERIAL CLOCK+ High Time 40 – ns Tsens Enable to Clock Delay Time 35 – ns Tsenh Clock to Disable Delay Time Delay from SERIAL CLOCK+ falling edge 100 – ns Tds Data Setup Time 15 – ns Tdh Data Hold Time 15 – ns Tdskewl Clock to Valid Data Delay Time Delay from SERIAL CLOCK+ falling edge –27 ns Tdskewe End of Valid Data to Clock – 0 ns Tsendl Time to Tri-stated SERIAL DATA I/O Delay from falling edge of SERIAL ENABLE –50 ns Tturnd SERIAL DATA I/O Turnaround Time 70 – ns Tsl SERIAL ENABLE Low Time 200 – ns (**) Bench test only. (***) Preliminary data. L6000 13/24 |
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