PIN DESCRIPTION (continued)

Pin #

Symbol

Type

Description

ANALOG

50

LEVEL REF V

O

REFERENCE VOLTAGE: Reference voltage output for LEVEL. LEVEL REF V

is derived by referencing VRG (an internal signal) to Vcc PULSE DET.

62

EF IREF

I

REFERENCE RESISTOR INPUT: An external 1% resistor (RX) is connected

from this pin to ground to establish a precise reference current for the filter.

3

DATA BYP

–

AGC INTEGRATING CAPACITOR: Connected between DATA BYP and Vcc

PULSE DET. This pin is used when data read mode.

48

SERVO BYP

–

AGC INTEGRATING CAPACITOR FOR SERVO: Connected between SERVO

BYP and Vcc PULSE DET. This pin is used when in servo read mode

45

HOLD CAP A

–

PEAK HOLDING CAPACITOR A: Tied from this pin to GND PULSE DET.

44

HOLD CAP B

–

PEAK HOLDING CAPACITOR B: Tied from this pin to GND PULSE DET.

49

LEVEL

O

HYSTERESIS LEVEL: An NPN emitter output that provides a full-wave

rectified signal from LEVEL to LEVEL REF V to set the hysteresis threshold

time constant in conjunction with SERVO TC RES and DATA TC RES. This

level used in VTHRESHOLD DAC.

33

DS IREF

I

REFERENCE RESISTOR INPUT: An external 1% resistor (RR) is connected

to this pin to establish a precise internal reference current for the data

separator and Frequency Synthesizer.

42

SERVO TC RES

I

SERVO TIME CONSTANT RESISTOR INPUT: An external resistor is

connected from this pin to LEVEL to establish the hysteresis threshold time

constant when not in Servo mode.

15, 16

FREQ SYN FLT,

FREQ SYN FLT

–

PLL FILTER: The two connection points for the frequency synthesizer PLL

differential filter components.

32, 31

DATA SEP FLT,

DATA SEP FLT

–

PLL FILTER: THE Two connection points for the data separatorPLL differential

filter components.

41

DAC TP OUT

O

DAC OUTPUT: A test point for some of the on-chip DACs. The output of an

internal DAC is selected by the values of TDAC1 (MSB) and TDACO (LSB) in

the WS register. The selected DAc output and its corresponding select bits are

as follows: FC_DAC (00), VTH_DAC (0 1), WS_DAC (1 0), and WP_DAC (1

1). When not using the DAC TP OUT pin, the preferred setting is to select the

FC_DAC.

SERIAL PORT

10

SERIAL ENABLE

I

SERIAL DATA ENABLE: Active high input pin to enable the serial port CMOS

input levels.

8

SERIAL DATA I/O

I/O

SERIAL DATA: Input/Output pin for serial data; 8 instruction/address bits are

sent first followed by 8 data bits. CMOS Input/Output levels.

9

SERIAL CLOCK+

I

SERIAL DATA CLOCK: Positive edge triggered clock input for the serial data

CMOS input levels. The pin has an internal pull-up resistor.

L6000

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