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L6000 数据表(PDF) 14 Page - STMicroelectronics |
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L6000 数据表(HTML) 14 Page - STMicroelectronics |
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14 / 24 page  MODE CONTROL PWRDN Mode Register bits DESCRIPTION X X X O X X X X X FULL POWER DOWN MODE : Only the serial interface remains operational. Switching from this mode to either Servo, Read or Idle modes initiates certain Read Channel states. Switching direct to Write modes is an illegal sequence. See Circuit Opertion. 0 1 1 1 0 0 0 0 0 READ MODE : The entire FRONT END is turned on, the READ DATA I/O pin is inactive, and the AGC amplifier is active, with unshorted inputs ( low-impedance mode off ) and in tracking mode. The HOLD DATA AGC input is enabled. The Data Separator section initiates its Address Mark search on the assertion of READ GATE. It then starts its phase lock up sequence aft er Address Mark detection occurs. After 3 ⋅ 3T following the Address Mark Detection the DS PLL is switched from Fout/2 to DRD and the look-in sequence is initiated. After 19 ⋅ 3T RRC switche from Fout/3 to DATA SYNCHRONIZER Vco/3 and NRZOUT is enabled. After. Read mode is maintained until the deassertion of READ GATE. 1 0 1 1 0 0 0 0 0 WRITE MODE : The FRONT END is inactive. The assertion of WRITE GATE causes the pin WRT DATA NRZ IN to become an active input, and the pins READ NRZ OUTPUT and ADDR MARK DET are floated. The inputs of both the Active filter and AGC amplifier are shorted ( i.e. the low- impedance state entered ). The PLL is locked to the Frequency Synthesizer divided by 30. n WRITE GATE assertion, two address marks ( each 7 0’s, 1, 7 0’s, 1, 11 0’s, 1, 11 0’s ) are generated and than the preamble of three 3T groups. WRT DATA NRZ IN must be zero until these patterns have been output from WRITE DATA. Write Mode is ended when Write Gate is deasserted. This starts the AGC Amplifier fast attack/decay currents acquisition, as well as unshorting the filter and AGC Amplifier inputs. 0 0 1 1 0 0 0 0 0 IDLE MODE : Allthe front end circuitry is active and operating. The Data Separator VCO is phase locked to Fout. The READ REF CLOCK outputs is the Frequency Synthesizer divided by 3. The pin READ NRZ OUTPUT is floated, ADDR MARK DET is high, READ DATA I/O is an active output of the pulses detected and HOLD DATA AGC is enabled. The inputs to the AGC Amplifier and filter are unshorted. 0 X 0 1 0 0 0 0 0 SERVO MODE 1 : The Pulse Detector and Servo Demodulator circuitry is operating, and the HOLD DATA AGC input is disabled. The Data Separator is on and it is phase locked to the Frequency Sinthesizer which is also on. The pin READ DATA I/O is an active output. 0 X 0 1 0 0 0 1 1 SERVO MODE 2 : This mode has both the Frequency Synthesizer and Data Separator major blocks powered down, otherwise it is the same as SERVO MODE 1 . This mode is intended to reduce power dissipation when the systhem is just track following. Since only the Pulse Detector and Active Filter are powered on, this is also known as FRONT END TEST MODE. L6000 14/24 |
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