L6000 datasheet(18/24 Pages) STMICROELECTRONICS

18 / 24 page

patible data pulse. The PD- Test bit of the register

CA controls this output being active. NORMAL

operation is for this bit to be reset , but for testing

the Data Separator as an input, it should be set.

Servo Demodulator

When in Servo mode all circuitry not needed to

acquire embedded servo position information is

deactivated, the AGC loop is switched to the

servo BYP capacitor, the READ DATA I/O output

is activated, the SERVO TC RES Servo time con-

stant setting resistor is connected to LEVEL REF

V, and the hysteresis threshold level is set to the

Servo threshold.

Three servo control inputs,

LATCH CAP A, LATCH CAP B, and RESET CAP

A/B

control the servo peak sample and hold

functions. When HOLD SERVO AGC is deas-

serted, the servo charge pump drives the SERVO

BYP hold capacitor. The current magnitude and

direction is determined by the formula :

Ibyp2 = gm1*( Vset-Va ( DIN ) pp-Vb ( DIN ) pp )

where : gm1 = 640 uA/Vpp

Vset = 1.0Vpp

Va/b( DIN ) pp = peak to peak A or B servo pat-

tern signal voltages across DATA PATH and

DATA PATH.

When SERVO GATE is deasserted, there is an

automatic 1 usec break before make switch in an

action before the capacitor on the DATA BYP pin

is reconnected to the AGC gain control.

The POSITION OUT pin outputs a voltage equal

to the difference beetwen HOLD CAP A and

HOLD CAP B referenced to SERVO REF V.

The DATA BYP and SERVO BYP capacitor volt-

ages will be held constant (subject to leakage cur-

rent) during sleep mode, when the respective

HOLD DATA AGC and HOLD SRV AGC signals

are low, and when they are not being used to

control the AGC loop.

Test bits and modes

The FDCT bit in the Control A register forces the

Charge pump into the fast decay (or 0.08 mA cur-

rent) mode. This bit should be set during power

up in a normal system. The PD_Test bit stands

for Pulse Detector Test and should be reset, so

that MULT TP1 outputs Delayed Read Data

(DRD), and MULT TP2 outputs the Data Separa-

tor VCO (divided by two).

Programmable Active Filter

The outputs of the AGC Amplifier of the Pulse De-

tector block are normally AC coupled to inputs of

the Active Filter. The low-pass portion of the ac-

tive filter is to bandlimit noise. The FCutoff regis-

ter is used to set the cutoff frequency of this por-

tion. The filter type is a 7 pole 0.05 degree

equiripple linear phase error low-pass. Shaping

response may also be introduced, via the boost

equalization available. This is done to account for

deficiencies in the recording process. The FBoost

the cutoff

frequency

in the Active Filter. The

amount set is contained in the FB register. The

boost is accomplished by a two pole high-pass

feed forward section in parallel with the low-pass

filter. A differentiator is also part of the Active Fil-

ter major block to turn the recovered peaks into

zero crossing. The differentiator is a single pole,

single zero active type. The Active Filter block has

2 outputs. One set is the differential outputs from

the low-pass/equalization portion. The other set is

the differential outputs of differentiator portion.

Both sets of the outputs have matched delays to

maintain timing integrity when re-entering the

Pulse Detector major block. The current reference

for the FC and FB DAC is developed off of the EF

IREF input. The recommended value of the resis-

tor at EF IREF is : 12 Kohm

±1% .

The normalized low-pass transfer function is :

(i.e.

ωc =2πfc = 1) are: (see Fig. 2 for reference)

Vnorm

= (

−Ks2 + 0.75928)

(s)

⋅ AN

The normalized differentiator transfer function is :

Vdiff

= (

−Ks2 + 0.75928) ⋅ s ⋅ 1.16099

)

⋅ AD

where D(s) = (1 + s + 1.27936 + s

2 0.75928)

⋅

(1 + s 0.52247 + s

2 0.33882)

⋅ (1 + s 0.21323 + s2

0.1862)

⋅ (1 + s 1.16099)

AN and AD are adjusted for a gain of 2 at fs =

(2/3)FC.

Frequency Synthesizer

The Frequency Synthesizer block is used to de-

velop source recording frequencies for writing

data in the system. It is Phase Lock Loop based

circuit with divide counters set by registers loaded

from the serial interface. The frequency gener-

ated, Fout, is 3 times the HOST data rate in

Mbits/sec, and is 2 times the CODE data rate of

pulses written on the disks. The resolution of the

frequency is 1%. The filter to the PLL is external,

and fully differential on the pins FREQ SYN FLT

and FREQ SYN FLT. A second order filter is rec-

ommended. The Fout frequency is used in Read,

Write and Idle modes as the reference for the

Data Separator PLL. If the ET bit of Control A reg-

ister is set in these modes the FRE OUT TP pin

will output the Synthesizer clock Fout. Setting this

bit in Read mode is not recommended in order to

reduce jitter and decrease power dissipation. To

set the frequency, the input REFERENCE FIN is

fed to the divide by N+1 counter, and this counter

output is the reference input of the Frequency

L6000

18/24

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