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L6000 数据表(PDF) 21 Page - STMicroelectronics |
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L6000 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 24 page  matically restart the Address Mark search. 2.Preamble is recognized upon the presence of three cycles of a 3T pattern. 3.Recognition of preamble switches phase de- tector input from the Fout divide by 2 refer- ence clock to delayed readback data (DRD) 4.The VCO is zero phase error restarted to the 3 x 3T readback pulse seen after switching of the phase detector input. 5.Depending on the state of the GS bit in the Control B register: If GS is set: a)The IC will count 8 more data bits (3T peri- ods) and then will decrease the charge pump current to 1/3 its lock up value. After 8 more data bits, the data Synchronizer starts to decode NRZ. The switchover for READ REF CLOCK from Fout divided by 3 to VCO divided by 3 is made, without glitches. If GS is reset: b) The IC will count 16 more data bits (3T periods) and the charge pump current is NOT changed. All operations as in GS set then occur. Decoding specifically starts later by 8 bits if GS is reset. 6.RRC clock is output from the pin READ REF CLOCK and decoded data is output from the pin READ NRZ OUTPUT until READ GATE deasserts. Hard Sector - Read Back In Hard Sector, the SOFT bit in Control B register has been reset. The lock up sequence procedees as follows: 1.An Address Mark is not searched for and ADDR MARK DET remains inactive. 2.Preamble is recognized upon the presence of three cycles of a 3T patern. 3.Recognition of preamble switches phase de- tector input from the Fout divide by 2 refer- ence clock to delayed readback data (DRD). 4.The VCO is zero phase error restarted to the first readback pulse seen after switching of the phase detector input. 5.The rest of the Read mode sequence is iden- tical to the Soft Sector submode. Window Shift Control Window shift magnitude is set by the value in the Window Shift (WS) register. The register bits are defined as follows: Bit Symbol Description 0 1 2 3 4 5 6 7 WSO WS1 WS2 WS3 WSD WSE TDACO TDAC1 Window Shift LSB Window Shift Window Shift Window Shift MSB Window Shift Direction Enable Window Shift Control Bit for DAC Testing Control Bit for DAC Testing WSD - Window Shift direction control 0 ≥ Early window (+TS) 1 ≥ Late window (-TS) Window Shift magnitude control bits: WS3 WS2 WS1 WS0 Shift Magnitude (% of the decode window) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 No shift 2% Minimum shift 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% 24% 26% 28% 30% Maximum shift for example the shift magnitude corresponding to 2% at 10 Mbit/s data rate is 0.667ns. This is 2% of TVCO since the decode window is 2*TVCO. Its tolerance is ±25%. WSE, WSD, WS3, WS2, WS1, and WS0 are programmed through the serial port during the idle or write mode. Write Mode Write mode takes WRT DATA NRZ IN and WRITE CLOCK as input, which this mode then encodes to (1,7) RLL format pulse stream. Again, there is a SOFT and HARD sector mode for Writes. WRITE GATE must be asserted no less than 1 RRC clock period AFTER READ GATE has been dessearted. This is to allow for clock deglitching. There is a register which becomes important only during Write Mode: the Write Pre- compensation register (R0D). If the WPE bit is set, the data being written to the disk will be pre- compensated by the magnitude specified, and ac- cording to the algorithm in the following Table. Soft Sector The write operation sequence is: 1.WRITE GATE input is asserted and WRT DATA NRZ IN should be a pattern of 80H or FFH followed by 8 bytes of 0. This is to allow L6000 21/24 |
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