PIN DESCRIPTION

Pin #

Symbol

Type

Description

POWER SUPPLY

30

Vcc DATA SEP

-

DATA SEPARATOR: PLL analog 5V supply.

14

Vcc FREQ. SYNTH

-

FREQUENCY SYNTHESIZER: PLL analog 5V supply.

7

Vcc CORE DIG

-

Internal ECL, CMOS logic digital supply.

19

Vcc I/O

TTL BUFFER I/O 5V SUPPLY.

59

Vcc PULSE DET

-

Pulse Detector/Servo Demodulator/Filter analog 5V supply.

34

GND DATA SEP

-

DATA SEPARATOR: PLL analog 5V ground.

12

GND FREQ SYN

-

FREQUENCY SYNTHESIZERl: PLL analog 5Vground.

40

GND CORE DIG

-

Internal ECL, CMOS logic digital ground.

23

GND I/O

-

TTL Buffer I/O digital ground.

5

GND PULSE DET

-

Pulse Detector/Servo Demodulator/Filter analog circuit ground.

INPUT

2, 1

AGC IN,

AGC IN

|

AGC AMPLIFIER INPUTS: Differential AGC amplifier input pins.

53, 54

DATA PATH,

DATA PATH

I

ANALOG INPUTS FOR DATA PATH: Differential analog inputs to data

comparators, full-wave rectifier, and servo demodulator.

51, 52

CLOCK PATH,

CLOCK PATH

I

ANALOG INPUTS FOR CLOCK PATH: Differential analog inputs to the clock

comparator.

6

PWRDN MODE

I

PWRDN MODE CONTROL: TTL compatible power control pin. Assertion shuts

down all circuitry, except the serial port. Deassertion and the appropriate bit set

in PD register shuts down the selected circuitry. Active low.

4

HOLD DATA AGC

I

HOLD DATA AGC CONTROL INPUT: TTL compatible power control pin.

Assertion disables the AGC charge pump and holds the input AGC amplifier

gain. Active low.

38

HOLD SRV AGC

I

HOLD DATA AGC CONTROL INPUT: TTL compatible control pin. Assertion

disables the SERVO charge pump. Active low.

47

SERVO REF V

I

SERVO REFERENCE .VOLTAGE INPUT: This voltage is set to half of the Vcc

PULSE DET voltage

37

LATCH CAP A

I

LATCH CONTROL INPUT: TTL compatible input. Switches channel A into

peak acquisition mode when low. Cap voltage doesn’t change when high.

36

LATCH CAP B

I

LATCH CONTROL INPUT: TTL compatible input. Switches channel B into

peak acquisition mode when low. Cap voltage doesn’t change when high.

35

RESET CAP A/B

I

RESET CONTROL INPUT: TTL compatible input. Enables the discharge of

channel A & B hold capacitors when asserted. Active low.

60, 61

FILTER IN,

FIL TER IN

I

FILTER SIGNAL INPUTS: Self biased differential input signals to active filter.

11

REFERENCE FIN

I

REFERENCE FREQUENCY INPUT: TTL input. Pin REFERENCE FIN has an

internal pull up resistor. In the test mode, when frequency synthesizer is

bypassed, the REFERENCE FIN frequency required is 3 times the data rate.

REFERENCE FIN may be driven by a direct coupled TTL signal.

22

WRT DATA NRZ

IN

I

WRITE DATA NRZ INPUT. TTL input. Connected to the READ NRZ OUTPUT

pin to form a bidirectional data port. Pin WRT DATA NRZ IN has an internal

pull up resistor.

17

READ GATE

I

READ GATE : See clocks and Modes.

26

WRITE CLOCK

I

WRITE CLOCK: TTL input Write mode clock. Must be synchronous with the

Write Data NRZ input. For short cable delays, WRITE CLOCK may be

connected directly to pin READ REF CLOCK. For long cable delays,WRITE

CLOCK should be connected to a READ REF CLOCK return line matched to

the NRZ data bus line delay.

18

WRITE GATE

I

WRITE GATE: TTL input. Enables the write mode. See Clocks and Modes.

39

SERVO GATE

I

SERVO GATE: TTL input. Enables the servo read mode. Active low.

L6000

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