STM32F427AI datasheet(136/240 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F427xx STM32F429xx

136/240

DS9405 Rev 12

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements for FT I/Os is shown in Figure 35.

RPU

Weak pull-up

equivalent

resistor(6)

All pins

except for

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

VIN = VSS

kΩ

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

710

RPD

Weak pull-

down

equivalent

resistor(7)

All pins

except for

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

VIN = VDD

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

710

CIO(8) I/O pin capacitance

1. Specified by design.

2. Tested in production.

3. With a minimum of 200 mV.

4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, refer to Table 56: I/O

current injection susceptibility

5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be

higher than the maximum value, if a negative current is injected on adjacent pins. Refer to Table 56: I/O current injection

susceptibility

6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series

resistance is minimum (~10% order).

7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the

series resistance is minimum (~10% order).

Hysteresis voltage between Schmitt trigger switching levels. Evaluated by characterization.

Table 57. I/O static characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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