ST7FLCD1 datasheet(53/95 Pages) STMICROELECTRONICS

部件名	ST7FLCD1

功能描述	8-bit MCU for LCD Monitors with 60 KBytes Flash,2 KBytes RAM, 2 DDC Ports and Infrared Controller

PDF	95 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

53 / 95 page

53/95

ST7FLCD1

I²C Single-Master Bus Interface

SDA/SCL Line Control

Transmitter mode: The interface holds the clock line low before transmission to wait for the

microcontroller to write the byte in the Data Register.

Receiver mode: The interface holds the clock line low after reception to wait for the microcontroller

to read the byte in the Data Register.

The SCL frequency (fSCL) is controlled by a programmable clock divider which depends on the I²C

bus mode.

When the I²C cell is enabled, the SDA and SCL ports must be configured as a floating open-drain

output or a floating input. In this case, the value of the external pull-up resistor used depends on the

application.

When the I²C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.

Figure 28: I²C Bus Protocol

Figure 29: I²C Interface Block Diagram

SCL

SDA

MSB

ACK

Stop Condition

Start Condition

Data Register (DR)

Data Shift Register

Clock Control Register (CCR)

Status Register (SR)

Control Register (CR)

SDAI

SCLI

Interrupt

Clock Control

Data Control

SCL

SDA

Control Logic

ST7FLCD1 数据表(PDF) 53 Page - STMicroelectronics

ST7FLCD1 数据表(HTML) 53 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

数据表下载