ST7FLCD1 datasheet(23/95 Pages) STMICROELECTRONICS

部件名	ST7FLCD1

功能描述	8-bit MCU for LCD Monitors with 60 KBytes Flash,2 KBytes RAM, 2 DDC Ports and Infrared Controller

PDF	95 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

23 / 95 page

23/95

ST7FLCD1

Reset

3.2

Watchdog or Illegal Opcode Access Reset

For more information about the Watchdog, please refer to Section 12: Watchdog Timer (WDG)

An Illegal Opcode reset occurs if the MCU attempts to execute a code that does not match a valid

ST7 instruction.

3.3

External Reset

The external reset is an active low input signal applied to the RESET pin of the MCU.

As shown in Figure 9, the RESET signal must remain low for a minimum of 1 µs.

An internal Schmitt trigger and filter provided at the RESET pin improve noise immunity.

3.4

Reset Procedure

At power-up, the MCU follows the sequence described in Figure 9.

Note:

Refer to Electrical Characteristics for values of tDDR, tOXOV, VTRH, VTRL and VTRM.

Figure 8: Reset Generation Diagram

Figure 9: Reset Timing Diagram

Low Voltage Detector

RESLVD

VDD

RESET

Watchdog

Illegal Opcode Access

External Reset

Reset

VDD

OSCIN

fCPU

FFFF

FFFE

RESET

Watchdog Reset

tDDR

tOXOV

4096 CPU

Clock Cycle

Delay

ST7FLCD1 数据表(PDF) 23 Page - STMicroelectronics

ST7FLCD1 数据表(HTML) 23 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

数据表下载