ST7FLCD1 datasheet(33/95 Pages) STMICROELECTRONICS

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ST7FLCD1

Clocks & Low Power Modes

6.1.4

Clock Signals

The root clock is divided by a factor of 3 to obtain the CPU clock (fCPU).

6.2

Power Saving Modes

The MCU offers the possibility to decrease power consumption at any time by software operation.

6.2.1

HALT Mode

HALT mode is the MCU lowest power consumption mode. Also, HALT mode also stops the

oscillator stage completely which is the most critical condition (the MCU cannot recover by itself).

For this reason, HALT mode is not compatible with the watchdog protection.

6.2.2

WAIT Mode

This is a low power consumption mode. The WFI instruction sets the MCU in WAIT mode. The

internal clock remains active but all CPU processing is stopped. However, all other peripherals still

run.

Note:

In WAIT mode, DMA (DDC A and DDC B) accesses are possible.

6.2.3

Exit from HALT and WAIT Modes

The MCU can exit HALT mode upon reception of an external interrupt on pins ITA or ITB. The

oscillator is then turned back on and a stabilizing time is necessary before releasing CPU operation

(4096 CPU clock cycles). After this delay, the CPU continues operation according to the cause of its

release, either by servicing an interrupt or by fetching the reset vector in case of reset.

During WAIT mode, the I bit from the Condition Code register is cleared, enabling all interrupts. This

leads the MCU to exit WAIT mode, the corresponding interrupt vector tois fetched, the interrupt

routine is executed and normal processing resumes.

A reset causes the program counter to fetch the reset vector. Processing starts as with a normal

reset.

Figure 14: Clock System Diagram

Table 8: Watchdog Compatibility

Watchdog

Executing HALT Instruction

Enabled

Generates an immediate reset

Disabled

Puts the MCU in HALT mode

OSC

fCPU and other peripherals

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