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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7FOXK2 数据表(PDF) 86 Page - STMicroelectronics |
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ST7FOXK2 数据表(HTML) 86 Page - STMicroelectronics |
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86 / 226 page  On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2 86/226 Figure 39. PWM signal from 0% to 100% duty cycle Dead time generation A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is required for half-bridge driving where PWM signals must not be overlapped. The non- overlapping PWM0/PWM1 signals are generated through a programmable dead time by setting the DTE bit. DTGR[7:0] is buffered inside so as to avoid deforming the current PWM cycle. The DTGR effect will take place only after an overflow. Note: 1 Dead time is generated only when DTE=1 and DT[6:0] ≠ 0. If DTE is set and DT[6:0]=0, PWM output signals will be at their reset state. 2 Half Bridge driving is possible only if polarities of PWM0 and PWM1 are not inverted, i.e. if OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be generated. 3 Dead Time generation does not work at 1msec timebase. COUNTER t FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh DCRx=000h DCRx=FFDh DCRx=FFEh DCRx=000h ATR= FFDh fCOUNTER Dead time DT 6:0 [] Tcounter1 × = |
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