ST7FOXK2 datasheet(35/226 Pages) STMICROELECTRONICS

35 / 226 page

ST7FOXF1, ST7FOXK1, ST7FOXK2

Supply, reset and clock management

35/226

These bytes are systematically programmed by ST.

6.1.2

Customized RC calibration

If the application requires a higher frequency accuracy or if the voltage or temperature

conditions change in the application, the frequency may need to be recalibrated. Two non-

volatile bytes (RCCRH_USER and RCCRL_USER) are reserved for storing these new

values. These two-byte area is Electrically Erasable Programmable Read Only Memory.

Note:

Refer to application note AN1324 for information on how to calibrate the RC frequency using

an external reference signal.

How to program RCCRH_USER and RCCRL_USER

To access the write mode, the RCCLAT bit has to be set by software (the RCCPGM bit

remains cleared). When a write access to this two-byte area occurs, the values are latched.

When RCCPGM bit is set by the software, the latched data are programmed in the

EEPROM cells. To avoid wrong programming, the user must take care to only access these

two-byte addresses.

At the end of the programming cycle, the RCCPGM and RCCLAT bits are cleared

simultaneously.

Note:

During the programming cycle, it is forbidden to access the latched data (see Figure 9).

Figure 9.

RCCRH_USER and RCCRL_USER programming flowchart

Note:

If a programming cycle is interrupted (by a reset action), the integrity of the data in memory

is not guaranteed.

Access error handling

If a read access occurs while RCCLAT=1, then the data bus will not be driven.

If a write access occurs while RCCLAT=0, then the data on the bus will not be latched.

READ MODE

RCCLAT=0

RCCPGM=0

WRITE MODE

RCCLAT=1

RCCPGM=0

READ BYTES

WRITE THE 2 BYTES

AT THEIR ADDRESS

START PROGRAMMING CYCLE

RCCLAT=1

RCCPGM=1 (set by software)

RCCLAT

CLEARED BY HARDWARE

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