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ST7FOXK2 数据表(PDF) 97 Page - STMicroelectronics |
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ST7FOXK2 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 226 page  ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals 97/226 Force update In order not to wait for the counterx overflow to load the value into active DCRx registers, a programmable counterx overflow is provided. For both counters, a separate bit is provided which when set, make the counters start with the overflow value, i.e. FFFh. After overflow, the counters start counting from their respective auto reload register values. These bits are FORCE1 and FORCE2 in the ATCSR2 register. FORCE1 is used to force an overflow on Counter 1 and, FORCE2 is used for Counter 2. These bits are set by software and reset by hardware after the respective counter overflow event has occurred. This feature can be used at any time. All related features such as PWM generation, Output Compare, Input Capture, One-pulse (refer to Figure 50: Dynamic DCR2/3 update in one pulse mode) etc. can be used this way. Figure 51. Force overflow timing diagram 10.2.4 Low power modes 10.2.5 Interrupts Note: The AT4 IC is connected to an interrupt vector. The OVF event is mapped on a separate vector (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction). FFF ARRx E04 E03 fCNTRx CNTRx FORCEx FORCE2 FORCE1 ATCSR2 register Table 35. Effect of low power modes on autoreload timer Mode Description Wait No effect on AT timer Halt AT timer halted. Table 36. Description of interrupt events Interrupt Event Event Flag Enable Control bit Exit from Wait Exit from Halt Exit from Active-Halt Overflow Event OVF1 OVIE1 Yes No Yes AT4 IC Event ICF ICIE Yes No No Overflow Event2 OVF2 OVIE2 Yes No No |
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