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ST7FOXK2 数据表(PDF) 180 Page - STMicroelectronics

部件名 ST7FOXK2
功能描述  8-bit MCU with single voltage Flash memory, SPI, I²C, ADC, timers
PDF  226 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7FOXK2 数据表(HTML) 180 Page - STMicroelectronics

Back Button ST7FOXK2 Datasheet HTML 176Page - STMicroelectronics ST7FOXK2 Datasheet HTML 177Page - STMicroelectronics ST7FOXK2 Datasheet HTML 178Page - STMicroelectronics ST7FOXK2 Datasheet HTML 179Page - STMicroelectronics ST7FOXK2 Datasheet HTML 180Page - STMicroelectronics ST7FOXK2 Datasheet HTML 181Page - STMicroelectronics ST7FOXK2 Datasheet HTML 182Page - STMicroelectronics ST7FOXK2 Datasheet HTML 183Page - STMicroelectronics ST7FOXK2 Datasheet HTML 184Page - STMicroelectronics Next Button
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Instruction set
ST7FOXF1, ST7FOXK1, ST7FOXK2
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11.1.2
Immediate mode
Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte
contains the operand value.
Imm
11.1.3
Direct modes
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two submodes:
Direct (Short) addressing mode
The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF
addressing space.
Direct (Long) addressing mode
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after
the opcode.
11.1.4
Indexed modes (No Offset, Short, Long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three submodes:
Indexed mode (No Offset)
There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space.
Indexed mode (Short)
The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE
addressing space.
MUL
Byte multiplication
SLL, SRL, SRA, RLC, RRC
Shift and rotate operations
SWAP
Swap nibbles
Table 60.
Instructions supporting inherent addressing mode (continued)
Instruction
Function
Table 61.
Instructions supporting inherent immediate addressing mode
Immediate Instruction
Function
LD
Load
CP
Compare
BCP
Bit compare
AND, OR, XOR
Logical operations
ADC, ADD, SUB, SBC
Arithmetic operations



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