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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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RZ/G2UL 数据表(PDF) 31 Page - Renesas Technology Corp |
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RZ/G2UL 数据表(HTML) 31 Page - Renesas Technology Corp |
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31 / 67 page  RZ/G2UL Group 3. Electrical Characteristics R01DS0486EJ0110 Rev.1.10 Page 31 of 67 Jun 16, 2025 3.5.3.2 eMMC host interface timing (HS-SDR) Table 3.24 eMMC Host Interface Timing (MMC HS-SDR 3.3-V Power Supply) Item Symbol Min. Max. Unit Figures SD0_CLK clock cycle tMMCPP 30.00 — ns Figure 3.9 SD0_CLK clock high level width tMMCWH 13.50 — ns SD0_CLK clock low level width tMMCWL 13.50 — ns SD0_CLK clock rise time tMMCLH — 3 ns SD0_CLK clock fall time tMMCHL — 3 ns SD0_CMD/SDDAT output delay tMMCODLY −4.50 4.0 ns SD0_CMD/SDDAT input set up time tMMCISU 5.5 — ns SD0_CMD/SDDAT input hold time tMMCIH 2.0 — ns SD0_CMD/SDDAT input data width tMMCIDW — — ns Table 3.25 eMMC Host Interface Timing (MMC HS-SDR 1.8-V Power Supply) Item Symbol Min. Max. Unit Figures SD0_CLK clock cycle tMMCPP 20.00 — ns Figure 3.9 SD0_CLK clock high level width tMMCWH 9.25 — ns SD0_CLK clock low level width tMMCWL 9.25 — ns SD0_CLK clock rise time tMMCLH — 2.45 ns SD0_CLK clock fall time tMMCHL — 2.45 ns SD0_CMD/SDDAT output delay tMMCODLY −2.00 2.50 ns SD0_CMD/SDDAT input set up time tMMCISU 4.00 — ns SD0_CMD/SDDAT input hold time tMMCIH 1.40 — ns SD0_CMD/SDDAT input data width tMMCIDW — — ns tMMCPP tMMCWL tMMCWH tMMCLH tMMCHL tMMCISU tMMCIH tMMCODLY(max) tMMCODLY(min) SD_CLK (output) SD_CMD, SD_D7 to SD_D0 (input) SD_CMD, SD_D7 to SD_D0 (output) Figure 3.9 eMMC Host Interface Timing (MMC Default/HS-SDR 1.8-V/3.3-V Power Supply) |
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