RZSLASHG2UL datasheet(48/67 Pages) RENESAS

48 / 67 page

RZ/G2UL Group

3. Electrical Characteristics

R01DS0486EJ0110 Rev.1.10

Page 48 of 67

Jun 16, 2025

3.5.10

Serial Sound Interface (SSIF-2) Access Timing

Table 3.37

SSIF-2 Timing

Item

I/O

Symbol

Min.

Max.

Unit

Figures

Output clock cycle

Output

64000

Figure 3.32

Input clock cycle

Input

—

Clock high

Bidirectional

tHC

—

Clock low

tLC

—

Clock rise time/clock fall time

Output

tRC/tFC

—

Setup time

Input

tSR

—

Figure 3.33,

Figure 3.34,

Figure 3.35

Hold time

tHR

—

SILRCK output delay time

Output

tDTR

−5

Data output delay time

(Noise canceler not in use)

tDTR

−5

Data output delay time

(Noise canceler in use)

tDTR

Note: AC access timing condition: drive ability 12mA, output load 30pF, slew rate = fast

SSIn_BCK

tHC

tLC

tRC

tFC

tO, tI

Figure 3.32

Bit Clock Input/Output Timing

SSIn_RCK (input),

SSIn_RXD,

SSI2_DATA (input)

SSIn_BCK

SSIn_RCK (output),

SSIn_TXD,

SSI2_DATA (output)

tHR

tSR

tDTR

Figure 3.33

Transmission and Reception Timing (SSIBCK Falling Output)

RZ/G2UL 数据表(PDF) 48 Page - Renesas Technology Corp

RZ/G2UL 数据表(HTML) 48 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载

链接网址

RZ/G2UL 数据表(PDF) 48 Page - Renesas Technology Corp

RZ/G2UL 数据表(HTML) 48 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表 下载

链接网址

数据表下载