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RZ/G2UL 数据表(PDF) 49 Page - Renesas Technology Corp |
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RZ/G2UL 数据表(HTML) 49 Page - Renesas Technology Corp |
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49 / 67 page ![]() RZ/G2UL Group 3. Electrical Characteristics R01DS0486EJ0110 Rev.1.10 Page 49 of 67 Jun 16, 2025 SSIn_RCK (input), SSIn_RXD, SSI2_DATA (input) SSIn_BCK SSIn_RCK (output), SSIn_TXD, SSI2_DATA (output) tHTR tSR tDTR Figure 3.34 Transmission and Reception Timing (SSIBCK Rising Output) tDTR Transmission data (MSB) SSIn_RCK (input) SSIn_TXD SSI2_DATA (output) Note: Output timing of the MSB when slave transmission satisfies the following condition a) or b) a) SSICR.DEL = 1, SSICR.SDTA = 0 b) SSICR.DEL = 1, SSICR.SDTA = 1, without padding Figure 3.35 Transmission Timing (Slave, in Synchronization with SSILRCK) |
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