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RZ/G2UL 数据表(PDF) 62 Page - Renesas Technology Corp |
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RZ/G2UL 数据表(HTML) 62 Page - Renesas Technology Corp |
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62 / 67 page ![]() RZ/G2UL Group 3. Electrical Characteristics R01DS0486EJ0110 Rev.1.10 Page 62 of 67 Jun 16, 2025 3.5.18 A/D Converter Access Timing Table 3.45 A/D Converter Timing Item Symbol Min. Max. Unit Figures ADC Trigger Input Pulse Width tTRGW 1.5*2 tP1cyc*1 Figure 3.50 Note 1. tp1cyc indicates peripheral clock means ADC_ADCLK (TSUϕ). Note 2. When a noise filter in ADC is off. ADC_TRG tTRGW Figure 3.50 ADC Trigger Input Timing 3.5.19 Watchdog Timer Access Timing Table 3.46 Watchdog Timer Timing Item Symbol Min. Max. Unit Figures WDTOVF_PERROUT# Output Time tL 64 64 tP1cyc*1 Figure 3.51 Note 1. tP1cyc indicates peripheral clock means WDTn_CLK (OSCCLK) (n = 0, 2). WDTOVF_PERROUT# tL Figure 3.51 Watchdog Timer Output Timing |
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