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RZ/G2UL 数据表(PDF) 24 Page - Renesas Technology Corp

部件名 RZ/G2UL
功能描述  RZ 32 & 64-bit MPUs, RZ/G Series
PDF  67 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

RZ/G2UL 数据表(HTML) 24 Page - Renesas Technology Corp

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RZ/G2UL Group
3. Electrical Characteristics
R01DS0486EJ0110 Rev.1.10
Page 24 of 67
Jun 16, 2025
Table 3.16
DC Characteristics (14) [DDR3L Cross Point Voltage For Differential Output Signals (CK/DQS)]
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
Differential output cross point voltage
relative to 0.5 × DDR_VDDQ
VOX(CK/DQS) −0.1
—
0.1
V
Table 3.17
DC Characteristics (15) [USB 2.0]
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
Input levels for low/full speed
High (driven)
VIH
2.0
—
—
V
Low
VIL
—
—
0.8
V
Differential input sensitivity
VDI
0.2
—
—
V
Differential common mode range
VCM
0.8
—
2.5
V
Input levels for high speed
High-speed squelch detection threshold
(differential signal amplitude)
VHSSQ
100
—
150
mV
High-speed data signaling common
mode voltage range (guideline for
receiver)
VHSCM
−50
—
500
mV
Output levels for low/full speed
Low
VOL
0.0
—
0.3
V
High (driven)
VOH
2.8
—
3.6
V
Output signal crossover voltage
VCRS
1.3
—
2.0
V
Output levels for high-speed
High-speed idle level
VHSOI
−10.0
—
10.0
mV
High-speed data signaling high
VHSOH
360
—
440
mV
High-speed data signaling low
VHSOL
−10.0
—
10.0
mV
Chirp J level (differential voltage)
VCHIRPJ
700
—
1100
mV
Chirp K level (differential voltage)
VCHIRPK
−900
—
−500
mV
Table 3.18
DC Characteristics (16) [ADC]
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
Resolution
—
—
12
—
Bit
Analog input channel
—
—
—
2
Channel
Analog input range
AIN
VSS
—
ADC_AVDD18
V
Differential non-linearity
DNL
—
—
±3.0
LSB
Integral non-linearity
INL
—
—
±6.0
LSB
Full-scale error
—
—
±10
±20
LSB
Offset error
—
—
±10
±20
LSB
Analog input capacitance
CIN
—
—
12.6
pF
Analog input resistance
RIN
—
—
1780
Ω
External capacitance
CEXT
—
—
(*1)
pf
External resistance
REXT
—
—
(*1)
Ω
Note 1.
Refer to
Figure 3.4 for Cext and Rext.
The Cext and Rext need to satisfy the sampling time.
A/D conversion time = sampling time (6T to 2800T) + 14T.
T stands for the cycle of ADIVCLK (20 MHz).
If A/D conversion is performed with the minimum conversion time, the sampling time must be 6T.
(Minimum conversion time per channel is 1 μs when A/D conversion clock ADIVCLK is 20 MHz.)



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