EM78P468NBQSSLASHNBQJ datasheet(20/82 Pages) EMC

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EM78P468N/L

8-Bit Microcontroller

•

Product Specification (V1.6) 12.31.2007

(This specification is subject to change without further notice)

Bit 4:

Not used

Bit 3 (IROUTE):

Define the function of P5.7/IROUT pin.

IROUTE = “0” :

for bi-directional general I/O pin.

IROUTE = “1” :

for IR or PWM output pin, the control bit of P5.7 (Bit 7 of IOC50)

must be set to “0”

Bit 2 (TCCE):

Define the function of P5.6/TCC pin.

TCCE = “0” :

for bi-directional general I/O pin.

TCCE = “1” :

for external input pin of TCC, the control bit of P5.6 (Bit 6 of IOC50)

must be set to “1”

Bit 1 (EINT1):

Define the function of P5.5/INT1 pin.

EINT1 = “0” :

for bi-directional general I/O pin.

EINT1 = “1” :

for external interrupt pin of INT1, the control bit of P5.5 (Bit 5 of

IOC50) must be set to “1”

Bit 0 (EINT0) :

Define the function of P5.4/INT0 pin.

EINT0 = “0” :

for bi-directional general I/O pin.

EINT0 = “1” :

for external interrupt pin of INT0, the control bit of P5.4 (Bit 4 of

IOC50) must be set to “1”

6.1.16 RF/ISR (Interrupt Status Register)

(Address: 0Fh)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ICIF

LPWTF

HPWTF

CNT2F

CNT1F

INT1F

INT0F

TCIF

These bits are set to “1” when interrupt occurs respectively.

Bit 7 (ICIF):

Port 6, Port 8, input status changed interrupt flag. Set when Port 6, Port 8

input changes.

Bit 6 (LPWTF):

interrupt flag of the internal low-pulse width timer underflow.

Bit 5 (HPWTF):

interrupt flag of the internal high-pulse width timer underflow.

Bit 4 (CNT2F):

interrupt flag of the internal Counter 2 underflow.

Bit 3 (CNT1F):

interrupt flag of the internal Counter 1 underflow.

Bit 2 (INT1F):

external INT1 pin interrupt flag.

Bit 1 (INT0F):

external INT0 pin interrupt flag.

Bit 0 (TCIF):

TCC timer overflow interrupt flag. Set when TCC timer overflows.

6.1.17 Address: 10h~3Fh; R10~R3F (General Purpose Register)

R10~R31F and R20~R3F (Banks 0~3) are general purpose registers.

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