EM78P468NBQSSLASHNBQJ datasheet(40/82 Pages) EMC

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EM78P468N/L

8-Bit Microcontroller

•

Product Specification (V1.6) 12.31.2007

(This specification is subject to change without further notice)

6.8 Interrupt

This LSI has eight interrupt sources as listed below:

TCC overflow interrupt.

External interrupt P5.4/INT0 pin

External interrupt P5.5/INT1 pin

Counter 1 underflow interrupt

Counter 2 underflow interrupt

High-pulse width timer underflow interrupt

Low-pulse width timer underflow interrupt

Port 6, Port 8 input status change wake-up

This IC has internal interrupts which are falling edge triggered or as follows:

TCC timer overflow interrupt

Four 8-bits down counter/timer underflow interrupt

If these interrupt sources change signal from high to low, the RF register will generate a

“1” flag to the corresponding register if the IOCF0 register is enabled.

RF is the interrupt status register. It records the interrupt request in flag bit. IOCF0 is

the interrupt mask register. Global interrupt is enabled by ENI instruction and disabled

by DISI instruction. When one of the interrupts (when enabled) is generated, it will

cause the next instruction to be fetch from address 0003H~0018H according to

interrupt source.

With this LSI, each individual interrupt source has its own interrupt vector as depicted in

Table 3. Before the interrupt subroutine is executed, the contents of the ACC and the

R3 register are initially saved by the hardware. After the interrupt service routine is

completed, the ACC and R3 are restored. The existing interrupt service routine does

not allow other interrupt service routine to be executed. Hence, if other interrupts occur

while an existing interrupt service routine is being executed, the hardware will save the

later interrupts. Only after the existing interrupt service routine is completed that the

next interrupt service routine is executed.

Fig. 6-13 Interrupt Back-up Diagram

ACC

STACKACC

STACKR3

Interrupt Source

ENI / DISI

Interrupt

Occurs

RETI

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